Design of the IBM Enterprise System/9000 high-end processor

Liptay, J. S.

doi:10.1147/rd.364.0713

Cited by 34 publications

(7 citation statements)

References 3 publications

(2 reference statements)

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“…This is the first System z core in two decades to execute instructions out of program order and is the most aggressive out-of-order System z core in terms of the number of instructions in flight and out-of-order instruction window size. The System z predecessor S/360 Model 91 pioneered out-of-order execution in the 1960s, and several generations of bipolar mainframes in the early 1990s employed out-of-order techniques [15]. The z196 processor design follows another generation of a deep-pipelining high-frequency z10 microprocessor design.…”

Section: Processor Microarchitecturementioning

confidence: 99%

IBM zEnterprise 196 microprocessor and cache subsystem

Busaba¹,

Blake²,

Curran³

et al. 2012

IBM J. Res. & Dev.

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The IBM zEnterprise A 196 (z196) system, announced in the second quarter of 2010, is the latest generation of the IBM System z A mainframe. The system is designed with a new microprocessor and memory subsystems, which distinguishes it from its z10 A predecessor. The system has up to 40% improvement in performance for traditional z/OS A workloads and carries up to 60% more capacity when compared with its z10 predecessor. The memory subsystem has four levels of cache hierarchy (L1 through L4) and constructs the L3 and L4 caches with embedded DRAM silicon technology, which achieves approximately three times the cache density over traditional static RAM technology. The microprocessor has 50% more decode and dispatch bandwidth when compared with the z10 microprocessor, as well as an out-of-order design that can issue and execute up to five instructions every single cycle. The microprocessor has an advanced branch prediction structure and employs enhanced store queue management algorithms. At the date of product announcement, the microprocessor was the fastest complex-instruction-set computing processor in the industry, running at a sustained 5.2 GHz, executing approximately 1,100 instructions, 220 of which are cracked into reduced-instruction-set computing-type operations, to achieve large performance gains in legacy online transaction processing and compute-intensive workloads.

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Section: Processor Microarchitecturementioning

confidence: 99%

IBM zEnterprise 196 microprocessor and cache subsystem

Busaba¹,

Blake²,

Curran³

et al. 2012

IBM J. Res. & Dev.

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“…The benefits of using a BTB to guide instruction fetching and prefetch instructions have been well documented [24][25][26][27][28]. Figure 15 shows the instruction spectrogram for cluster sizes = 1, 2, 3, and 4 for oltp3.…”

Section: Instruction Spectrogrammentioning

confidence: 99%

Pipeline spectroscopy

Puzak

Hartstein

Emma

et al. 2007

Proceedings of the 2007 Workshop on Experimental Computer Science

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Pipeline Spectroscopy is a new technique that allows us to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogram, which represents a precise readout showing a detailed visualization of the cost of each cache miss throughout all levels of the memory hierarchy. We call the graphs 'spectrograms' because they reveal certain signature characteristics of the processor's memory hierarchy, the pipeline, and the miss pattern itself. We show that in a memory hierarchy with N cache levels (L1, L2, ..., L N , and memory) and a miss cluster of size C, there are C + N C possible miss penalties. This represent all possible sums from all possible combinations of the miss latencies from each level of the memory hierarchy (L2, L3, ... Memory) for a given cluster size. Additionally, a theory is presented that describes the shape of a spectrogram, and we use this theory to predict the shape of spectrograms for larger miss clusters. Detailed analysis of a spectrograph leads to much greater insight in pipeline dynamics, including effects due to prefetching, and miss queueing delays.

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“…The memory hierarchy modeled was a 64KB L1, 256KB L2 15 cycles away, 1MB L3 75 cycles away, and 300 cycle memory. Instruction fetching uses a 32K-entry branch target buffer (BTB) that runs well ahead of instruction fetching and the decoder, prefetching instructions [1]. Figure 2 shows the instruction spectrogram for cluster sizes = 1, 2, 3, and 4.…”

Section: Instruction Miss Spectrogrammentioning

confidence: 99%