The IBM POWER6e microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.
The multiplier of a S/390 CMOS microprocessor is described. It is implemented in an aggressive static CMOS technology with 0.20 p m effective channel length. T h e multiplier has been demonstrated in a single-image shared-memory multiprocessor at frequencies up t o 400 MHz. T h e multiplier requires three m achine cycles f o r a total latency of 7.5 ns. Though, the design can support a latency of 4.0 n s if the latches are removed. T h e design goal was t o implement a versatile S/390 multiplier with reasonable performance at a very aggressive cycle time. T h e multiplier implements a radiz-8 Booth algorithm and is capable of supporting S/390 floating-point and fixed-point multiplications and also division and square root. Logic design and physical design issues are discussed relating t o the Booth decode and counter tree implementations.
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