IBM POWER6 microprocessor physical design and design methodology

Berridge, R.; Averill, R.M.; Barish, A. E.; Bowen, Mark; Camporese, P. J.; DiLullo, Jack; Dudley, P.; Keinert, Joachim; Lewis, Daniel W.; Morel, Rolf; Rosser, Thomas; Schwartz, Nicole; Shephard, P.; Smith, H.; Thomas, Donald E.; Restle, P.J.; Ripley, J.; Runyon, Steve; Williams, Paul

doi:10.1147/rd.516.0685

Cited by 26 publications

(15 citation statements)

References 15 publications

(32 reference statements)

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“…From a die with hundreds of transistors in the 1960s to dies approaching billions of circuits in 2014, on-chip integration has continued to require lithographic advancements for circuit and increase in wire density has led to increasing the number of wiring levels on the chip. Over decades of semiconductor scaling, on-chip integration has far [20][21][22]. Figure 2.5 shows the evolution of 3D-IC technology along with the resulting relative I/O interconnection density for 3D design and implementation.…”

Section: Historical Evolution Of 3d System Integrationmentioning

confidence: 99%

Three-Dimensional Integration: A More Than Moore Technology

Pangracious

Marrakchi²,

Mehrez

2015

Lecture Notes in Electrical Engineering

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Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals and offer a promising solution for reducing both silicon footprint and interconnect length without shrinking the transistors. However, before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed. More specifically, the process required to build circuits with multiple layers of active devices and CAD tools used for design and validation of such circuits. Several such methodologies and CAD tools associated with the design fabrication of 3-D ICs are discussed in this chapter. Few successful 3D-IC design methods and CAD tools and benefits of applying 3D design to the future reconfigurable systems are also discussed in this chapter. IntroductionThe ongoing demand for greater functionality resulting in multiple IC products, longer off-chip interconnects ravage the performance of microelectronic systems. The advent of System-on-Chip (SoC) in the mid 1990s primarily addressed the increasing delay of the off-chip interconnects. Integrating all of the components on a monolithic substrate enhances the overall speed of the system, while decreasing the power consumption. To assimilate disparate technologies, however several difficulties must be surmounted to achieve high yield for the entire system. Additional system requirements for the radio frequency (RF) circuitry, passive elements, and discrete components, such us decoupling capacitors, which are not easily integrated due to performance degradation or size limitations. While Moore's law [1] and the pursuit of ever increasing transistor counts is well known in IC design and manufacturing circles, what is seldom brought to light for others, are the escalating cost and technology challenges associated with this pursuit. Smaller transistors and larger dies have been reasonable answer to this quest in the past. Stacked dies using wire bond connections and flip-chips have even been employed to create system-in-package (SiP) solutions that meet the needs of some. Looking for alternative solutions for next generation designs, that meet the performance, integration, form-factor, manufacturability, and cost requirements, may have begun to look at going up rather than out. With this trend, the Three-dimensional (3D) integration using through-silicon via (TSV) technology has gained much attention. Once the domain of specialist applications, more mainstream users, such as memories, microprocessors ans specialized logic designs are now being considered as TSV candidates. The advantages of 3D-IC integration are better electrical performance, low power consumption, lower area and weight and high performance (Fig. 2.1). Opportunities for Three-Dimensional IntegrationPerformance requirements such as increased band...

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Section: Historical Evolution Of 3d System Integrationmentioning

confidence: 99%

Three-Dimensional Integration: A More Than Moore Technology

Pangracious

Marrakchi²,

Mehrez

2015

Lecture Notes in Electrical Engineering

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“…Moreover, each additional core consumes incremental die area. The issue is not chip [22]. Therefore, the main reason must lie in the complexity and design effort added cores introduce to the interconnection network and cache hierarchy, in addition to a limited power budget.…”

Section: Increasing Concurrencymentioning

confidence: 99%

Core-Selectability in Chip Multiprocessors

Najaf-abadi

Choudhary

Rotenberg

2009

2009 18th International Conference on Parallel Architectures and Compilation Techniques

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The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip multiprocessors (CMP). The reason for this is that scaling these structures does not enhance general performance as much as scaling the cache and interconnect. However, the fact that these structures now consume less proportional die area opens an avenue to enhancing their performance through truly overcoming the one-size-fits-all approach to their design. This paper proposes core-selectability -incorporating differently-designed cores that can be toggled into active employment. This enables differently customized ILP-extracting structures to be at hand in the system while not dramatically adding to the interconnect complexity. The design verification effort is minimized by separating the complexity of different core designs. Moreover, contrary to alternative approaches, the performance and power efficiency of the core designs are not compromised. Evaluation results are presented that show that, even when limiting the diversity between core designs to only the sizing of microarchitectural structures, core-selectability has the potential to provide notable performance enhancement (with an average of 10%) to scalable multithreaded applications, without increased concurrency. In addition, it can provide significantly greater throughput to multiprogrammed workloads by providing the potential for the system to transform into a heterogeneous design.

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“…New opportunities are being brought to datacom, telecom, and high performance computing by this technology [1][2][3][4][5][6][7][8][9][10]. However, the large scale commercialization of silicon photonics still requires more cost effective optical inputs and output methods.…”

Section: Introductionmentioning

confidence: 99%

Nanofiller based spin-on materials for negligible reflection of silicon photonic external coupling

Taira

Mizusawa

Matsumoto

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Optical out coupling is one of the key research items of silicon photonic packaging. It is necessary to realize robust, high-bandwidth, low-power optical data communication system in an economical way. Because material interfaces are always involved for the coupling, the reflection loss at the interface often occupies a major part of loss. Here we report on an ideal anti-reflection coating method for use with silicon nanophotonics devices. Because the refractive index of silicon is large at about 3.5, the optical reflection at the silicon waveguide boundary is large. We describe a set of nanoparticle-based spin-on materials having indices of 1.8 and 1.2. The former material is suitable for a single layer antireflection coating on a silicon surface and realizes a first order thin reflection suppression which allows large bandwidth and large angle tolerance. The latter material is for coating of the fiber or polymer interface. We studied the feasibility of uniform coating over microlens structures. High index material is also photo patternable, which is desirable for silicon chip integration. IntroductionSignificant progress has been made in silicon nanophotonics technology. New opportunities are being brought to datacom, telecom, and high performance computing by this technology [1][2][3][4][5][6][7][8][9][10]. However, the large scale commercialization of silicon photonics still requires more cost effective optical inputs and output methods. Although there are several potential methods to realize these couplings, the methods have to satisfy the condition of spectral wide band, optical low loss, mechanical reliability, and cost efficiency.There are several approaches that enable the optical coupling between optical waveguides on a silicon photonics chip and an external single mode (SM) optical cable. Current approaches to interfacing silicon nanophotonic waveguides to standard single-mode fibers often use specialized equipment and show significant cost as well as scalability questions [11][12][13][14][15].

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IBM POWER6 microprocessor physical design and design methodology

Cited by 26 publications

References 15 publications

Three-Dimensional Integration: A More Than Moore Technology

Three-Dimensional Integration: A More Than Moore Technology

Core-Selectability in Chip Multiprocessors

Nanofiller based spin-on materials for negligible reflection of silicon photonic external coupling

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