Here, a facile route to fabricate thin ferroelectric poly(vinylidene fluoride) (PVDF)/poly(methylmethacrylate) (PMMA) blend films with very low surface roughness based on spin‐coating and subsequent melt‐quenching is described. Amorphous PMMA in a blend film effectively retards the rapid crystallization of PVDF upon quenching, giving rise to a thin and flat ferroelectric film with nanometer scale β‐type PVDF crystals. The still, flat interfaces of the blend film with metal electrode and/or an organic semi‐conducting channel layer enable fabrication of a highly reliable ferroelectric capacitor and transistor memory unit operating at voltages as low as 15 V. For instance, with a TIPS‐pentacene single crystal as an active semi‐conducting layer, a flexible ferroelectric field effect transistor shows a clockwise I–V hysteresis with a drain current bistability of 103 and data retention time of more than 15 h at ±15 V gate voltage. Furthermore, the robust interfacial homogeneity of the ferroelectric film is highly beneficial for transfer printing in which arrays of metal/ferroelectric/metal micro‐capacitors are developed over a large area with well defined edge sharpness.

A flexible field-effect transistor with a poly(3-hexylthiophene) (P3HT) active channel and a ferroelectric poly(vinlyidene fluoride-co-trifluoro ethylene) (PVDF-TrFE) insulator exhibits gate-voltage-controllable multilevel non-volatile memory characteristics with highly reliable data retention and endurance.

We demonstrate significantly improved performance of a nonvolatile polymeric ferroelectric field effect transistor (FeFET) memory using nanoscopic confinement of poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) within self-assembled organosilicate (OS) lamellae. Periodic OS lamellae with 30 nm in width and 50 nm in periodicity were templated using block copolymer self-assembly. Confined crystallization of PVDF-TrFE not only significantly reduces gate leakage current but also facilitates ferroelectric polarization switching. These benefits are due to the elimination of structural defects and the development of an effective PVDF-TrFE crystal orientation through nanoconfinement. A bottom gate FeFET fabricated using a single-crystalline triisopropylsilylethynyl pentacene channel and PVDF-TrFE/OS hybrid gate insulator shows characteristic source-drain current hysteresis that is fully saturated at a programming voltage of ±8 V with an ON/OFF current ratio and a data retention time of approximately 10(2) and 2 h, respectively.

No abstract

A new type of nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (P(VDF‐TrFE)) memory based on an organic thin‐film transistor (OTFT) with a single crystal of tri‐isopropylsilylethynyl pentacene (TIPS‐PEN) as the active layer is developed. A bottom‐gate OTFT is fabricated with a thin P(VDF‐TrFE) film gate insulator on which a one‐dimensional ribbon‐type TIPS‐PEN single crystal, grown via a solvent‐exchange method, is positioned between the Au source and drain electrodes. Post‐thermal treatment optimizes the interface between the flat, single‐crystalline ab plane of TIPS‐PEN and the polycrystalline P(VDF‐TrFE) surface with characteristic needle‐like crystalline lamellae. As a consequence, the memory device exhibits a substantially stable source–drain current modulation with an ON/OFF ratio hysteresis greater than 103, which is superior to a ferroelectric P(VDF‐TrFE) OTFT that has a vacuum‐evaporated pentacene layer. Data retention longer than 5 × 104 s is additionally achieved in ambient conditions by incorporating an interlayer between the gate electrode and P(VDF‐TrFE) thin film. The device is environmentally stable for more than 40 days without additional passivation. The deposition of a seed solution of TIPS‐PEN on the chemically micropatterned surface allows fabrication arrays of TIPS‐PEN single crystals that can be potentially useful for integrated arrays of ferroelectric polymeric TFT memory.

High-performance non-volatile memory that can operate under various mechanical deformations such as bending and folding is in great demand for the future smart wearable and foldable electronics. Here we demonstrate non-volatile solution-processed ferroelectric organic field-effect transistor memories operating in p-and n-type dual mode, with excellent mechanical flexibility. Our devices contain a ferroelectric poly(vinylidene fluoride-cotrifluoroethylene) thin insulator layer and use a quinoidal oligothiophene derivative (QQT(CN)4) as organic semiconductor. Our dual-mode field-effect devices are highly reliable with data retention and endurance of 46,000 s and 100 cycles, respectively, even after 1,000 bending cycles at both extreme bending radii as low as 500 mm and with sharp folding involving inelastic deformation of the device. Nano-indentation and nano scratch studies are performed to characterize the mechanical properties of organic layers and understand the crucial role played by QQT(CN)4 on the mechanical flexibility of our devices.

Polymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 104 s and 120 cycles, respectively.

Single crystalline triisopropylsilylethynyl pentacene (TIPS‐PEN) arrays are fabricated with both size and shape of each patterned domain precisely tailored by selective contact evaporation printing (SCEP), which exhibit sufficient ON/OFF current ratio as well as high field effect mobility.