This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pattern generator, a fault simulator and a fault list generator. The fault list generator uses a library-based fault modeling strategy which allows the specif cation of realistic target fault sets. Experimental results show that CONTEST can eficiently handle non-classical faults on the gate level. For a complex target fault set which encompasses for example stuck-at, stuck-open and bridging faults, a test eficiency of 100% has been achieved for each of the ISCAS benchmark circuits containing up to 38,000 nodes.
Based on 2jum-wide CoSi 2 -n'-and TiSi 2 -n+-polycide structures with a 100nm-thick silicide and a standard AlSi-metallization a comparison between conventional and the high accelerated SWEAT-test was carried out. Supported by simulations different parameters (e.g. activation energie EA) were determined by time-to-failuremeasurements. Because of comparable results out of both different tests the SWEATtest will be prefered due to short time-to-test. Also it will be shown that both silicide systems have an about three times higher activation energy for the inducing of EMbased "open"-failures than the tested standard AlSi-metallization. The failure-rate was less than 100 FIT for both polycides but because of process advantages the CoSi 2 -polycide should be a promissing metallization to improve the reliability of single and/or multilevel-metallization.
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