Deterministic test generation for non-classical faults on the gate level

Abstract

This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pattern generator, a fault simulator and a fault list generator. The fault list generator uses a library-based fault modeling strategy which allows the specif cation of realistic target fault sets. Experimental results show that CONTEST can eficiently handle non-classical faults on the gate level. For a complex target fault set which encompasses for example stuck-at, stuck-open and bridging faults, a test eficiency of 100% has been achieved for each of the ISCAS benchmark circuits containing up to 38,000 nodes.

Mixed-level identification of fault redundancy in microprocessors

“…Further advancements of the low-level fault modeling have been achieved by introducing the fault tuple fault model [16], realistic sequential cell fault model [17], or cell-internal defect model [18], where the last two cases provide general capability to handle sequential misbehavior of circuits. The conditional SAF model (and other listed models) [8][9][10][11][12][13][14][15][16][17][18] support hierarchical test approach, where the test pattern (or sequence), which activates a low-level fault (e.g. physical defect) at the lower level can be considered as the high-level condition (or constraint) for the functional fault defined at the higher level.…”

“…In [12], a similar model called conditional faults was proposed for test generation purposes, and in [13] for diagnosis purposes. A conditional fault allows additional signal line objectives to be combined with the detection requirements of a particular fault.…”

“…The conditional SAF model (and other listed models) [8][9][10][11][12][13][14][15][16][17][18] support hierarchical test approach, where the test pattern (or sequence), which activates a low-level fault (e.g. physical defect) at the lower level can be considered as the high-level condition (or constraint) for the functional fault defined at the higher level.…”

“…Fig.1. Generic DNF based control structure of ALUThe proposed fault model can be regarded as a generalization of the conditional SAF model (or similar ones considered in[8][9][10][11][12][13][14][15][16][17][18]). In case of conditional SAF, we are testing SAF on the gate-level lines at some constrained signals on other lines, whereas in case of the high-level fault model of Definition 2, we are testing the instructions of microprocessors at a set of constraints for data (operands).Let us compare the complexities of the proposed highlevel control fault model and the traditional SAF model of the control part architecture in Fig.1.…”

Hierarchical physical defect reasoning in digital circuits

“…In [ 17 ], a similar model, called conditional faults, was proposed for test generation purposes, and in [ 18 ] for diagnosis purposes. A conditional fault allows additional signal line objectives to be combined with the detection requirements of a particular fault or physical defect.…”