Extreme ultraviolet lithography (EUVL) has been developed and studied for a sub-22 nm semiconductor device. It is difficult to obtain a smooth sub-22 nm pattern because line edge roughness (LER) and linewidth roughness (LWR) cannot be controlled well. According to the 2008 ITRS roadmap, LER has to be below 1.3 nm to achieve a 22 nm node for EUVL. In our previous work, the resist reflow process (RRP), in which the resist is baked above the glass transition temperature (T g ), was very helpful for reducing LER and LWR for EUVL. LER and LWR could be decreased from 6 to 1 nm. As RRP time progresses, however, the critical dimension could become wider because the developed resist can flow more easily when the temperature is above T g . Therefore, another method is suggested to solve this problem. The developed resist, which is intentionally designed with a 1 : 3 line and space (L/S) (11 : 33 nm) pattern, is baked above T g . As a result, LER and LWR can be smoothed by RRP and we could achieve a 22 nm 1 : 1 L/S pattern with a small LER. #
The purpose of extreme ultraviolet (EUV) lithography is to make pattern size of sub-22 nm. However, there are still some challenges to be overcome for EUV photoresist such as reducing the line edge roughness (LER) and line width roughness. The roughness of conventional polymer resists is large because of large polymer size. Thus many new molecular resists are studied and being developed in order to reduce roughness. To reduce LER we analyzed the size and structure of each ingredient of the suggested molecular resists. The varied parameters are the amount of photo acid generator, quencher and the size of the monomer. The protecting ratio of resin and protected number of a molecule are also varied. Monte-Carlo simulation is used for ingredient dispersion and acid diffusion direction to see the effect to LER. Solid-EUV is used to get the aerial image and photo generated acid for 22 nm node and ChemOffice is used to analyze molecular structure and volume.
In this article, an analysis of a failure in the embedded SRAM in a CMOS Image Sensor is investigated. The failure was due to unformed CoSi2. Because unformed CoSi2 causes a varying degree of response, a nano-prober was used to find the abnormally operating transistors among a 1-bit SRAM cell consisting of six transistors(6T). After measuring and analyzing the current-voltage relationships between each transistor, the current magnitude of one pull-down transistor was found to be less than the expected range and particularly lower than that of a connected access transistor. To visualize the failure phenomenon and find the root cause of this, TEM analysis was conducted. Using the EELS (Electron Energy Loss Spectroscopy) elemental mapping, unformed CoSi2 was detected between the contact and substrate, where the contact corresponds to the VSS of the pull-down transistor. This caused an increase in the contact resistance, thus lowering the current magnitude of the abnormal transistor to a greater degree than expected.
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