The rapid diversification in microelectronics forebodes more complex system integration, be it for denser function integration or a span of dimensions between various technologies. Products may include more features, perform faster and be cheaper. With these trends the amount of material layers is increasing. This challenges development to a faster rating of material pairings. Delamination is a major issue among the related reliability aspects. When the design or testing steps are accompanied by simulation, fracture mechanical descriptions are increasingly proving helpful. The parameters needed for simulation have to be measured and should be available for different fracture mode mix angles. We investigated the interfacial fracture toughness of the Epoxy Molding Compound (EMC) to Silicon interface. Although difficult to delaminate we could carry out measurements using the Mixed Mode Chisel setup (MMC) that allowed us to induce different stress states at the crack tip at various external load angles. The samples we derived from the molding process of embedded wafer level ball grid arrays. Therefore we were able to use samples made with the same process as in real packaging. The crack tip position was determined by analysis of displacement results by digital image correlation. In order to interpret the sample reaction for extracting fracture mechanical parameters, adequate numerical modeling and simulation was required. The experiments provided the parameters for the models. Establishing the residual stress state in the materials preceded the interface delamination simulation: a two step interpretation. Residual stresses cannot be neglected; indeed they are part of the challenges to delaminate this interface at all. We found energy release rates increasing with fracture mode mix, and such values close to pure tensile opening at the crack tip. We recommend to exclude data from short crack lengths and to carefully expose the sample flanks. The results promise to extend - - the available interfacial fracture data soon
Interface fracture mechanics is one of the main focuses of electronics reliability research. Determination of fracture mechanical properties of interface cracks is a substantial task for design for reliability comcept. Without experimental determined fracture mechanical parameters such as the critical energy release rate a reliability forecast based on simulation results cannot be given. In fracture mechanics testing often a correct measurement of the crack tip location is needed for the calculation of the energy release rate. The authors present a combined simulative and experimental method for crack tip location determination of typical interface specimens. The specimens are loaded in a newly designed testing apparatus, the Mixed Mode Chisel (MMC) setup, and images of the crack tip at the interface are taken at different load states during the testing procedure. Then images are analyzed by image correlation techniques (DAC, deformation analysis by correlation) and cra ck tip displacement fields are determined. In the next analysis step the displacement fields are compared to fields from finite element analysis of the same specimen geometry with boundary conditions similar to the experimental setup. The point of the best matching of the experimental and simulative field is the actual crack tip location. If finite-element data or analytical solution for the crack tip displacement field is available the method can be applied for a variety of different interface samples
This paper presents a comprehensive method for obtaining urgently required critical interface delamination data of material pairings used in electronic packaging. The objective is to thereby enable rapid, inexpensive and accurate lifetime prediction for that failure mode. A new testing method is presented which allows maximum mode-angle range and enhanced throughput testing under multiple loading conditions, the coverage of which is usually a rather lengthy and resource-demanding procedure. The approach is specimen-centred in the sense that the accent is put on test-specimens which are easily manufacturable industrially, rather than having to adapt them to a special testing machine. The concept is also scalable, i.e. it has potential to work also for smaller samples cut from real devices. We show the first version of a newly developed test-stand and discuss the obtained results for copper-molding compound interfaces in the light of the current state of the art used for delamination testing in electronic packaging
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