We present GAD, a compiler for arithmetic datapaths, i.e., systems Characterized by the absence of conditional branches and abundance of arithmetic operations. GAD'a inputs are the functional specification of the datapath in the form of a signal flow graph, as well as the required throughput rate. A netlist is generated for the synthesized datapath, which is optimized for the number of gates used.The synthesis problem is formulated into two parts: (1) Pipeline design, where machine cycles are organized into pipeline stages according to operator delays.(2) Scheduling, where operators are assigned to cycles so as to mazimize resource sharing. Heuristics have been developed for these problems which, by ezploiting the characteristics of arithmetic datapaths, manage t o systematically and efficiently ezplore a large part of the design apace.
A b s t r a c t Thi5 paper presents GAD, a synthesis tool for ASIC DS1' systems. Given the signal flow graph, the required 5y5lcm throughput, and a number of other optimization paramcters, GAD produces the gate level implementation of the system, which is optimized according to the total gate count of the realization. The types of DSP systems t argrted are arithmetic datapaths without conditional I~ranches and simple in control. GAD tries to maximize r('source sharing during scheduling to reduce cost. A iiiiiii bcr of cost-saving design techniques for DSP systems Iiavr also been encapsulated as independent optimization procedures. GAD is linked to the design of actual silicon t Iirough module generators that provide information on llic dcl:iys, gate counts, and netlists of the modules.
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