Synthesis of optimized ASIC DSP systems

Abstract

A b s t r a c t Thi5 paper presents GAD, a synthesis tool for ASIC DS1' systems. Given the signal flow graph, the required 5y5lcm throughput, and a number of other optimization paramcters, GAD produces the gate level implementation of the system, which is optimized according to the total gate count of the realization. The types of DSP systems t argrted are arithmetic datapaths without conditional I~ranches and simple in control. GAD tries to maximize r('source sharing during scheduling to reduce cost. A iiiiiii bcr of cost-saving design techniques for DSP systems Iiavr also been encapsulated as independent optimization procedures. GAD is linked to the design of actual silicon t Iirough module generators that provide information on llic dcl:iys, gate counts, and netlists of the modules.