This paper presents a novel design flow for threedimensional (3D) heterogeneous system prototyping platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. Based on system partition and tri-state interface connecting, the MorPACK system can be efficiently extended by system bus interfaces and can improve the functions by only updating the bare die/module. In addition, the total silicon prototyping cost of heterogeneous SoC projects can be greatly reduced by sharing the MorPACK common system platform. To demonstrate the effectiveness of the proposed platform, six SoC projects are implemented. The results show that there are 79.13% fabrication cost reduced by the MorPACK platform in TSMC 90nm CMOS. Besides, around 60% performance improvement of operation frequency can be benefited.Index Terms-3D Heterogeneous Integrated Platform, Mor-PACK, Platform-based Design I. INTRODUCTIONWith the fast advance of IC fabrication and electronic design automation (EDA) technologies, the system-on-a-chip (SoC) design technology has become more and more practical. A complex system can be integrated into a single chip through SoC design methodology and then achieves lower power consumption, lower cost, and higher speed than the traditional system on board design. Among the existing SoC design methodologies, the platform-based methodology [1] is the most off-the-shelf one. In this way, a platform is defined as an architectural framework consisting of a set of pre-qualified software and hardware IPs, which were integrated into some specific on-chip connection architecture.The platform-based design methodology is helpful for SoC implement. However, most of silicon areas expensed on the platform elements include processor, memory, bus, controller, or I/O. However, the user's IPs or special hardware accelerator designs of the projects/designs consume a few silicon areas. Therefore, in order to reduce the fabrication cost of SoC implement, an innovative Multi-Project System-on-a-Chip (MPSoC) design service model was developed. Although the MPSoC concept greatly reduces fabrication cost, however it is impractical to integrate the heterogeneous designs into a single system and the additional efforts of isolation mechanism need to be taken to prevent the interferences from other SoC projects in MP-SoC design. Besides, the efforts to integrate and implement the multi-projects into a single chip are relatively high.
We present an automatic interface synthesis system to expedite the IP (silicon intellectual property) integration process in SoC designs.The concept of multi-layer communication protocols is incorporated into the synthesis process so that interface design targeting different levels of functionality and circuit complexity can be generated automatically. The multi-layered interface architecture template designs are addressed in the first place. We then outline the methodology of interface synthesis, which includes protocol specifications, signal mapping & timing adjustment, interface FSM, and architecture mapping. Interface designs for several benchmark systems are developed using different synthesis options. Besides the advantage of greatly shortened design cycle, the experimental results do show the competitiveness of the automatically generated designs against the manual designs.
The present SoC prototyping platforms in the market are usually with stationary connecting architecture, including designated bus protocols and peripheral interfaces. Due to the lack of architectural flexibility, users are not allowed to adapt the architecture for specific applications by on-chip-buses and on-chip-networks. In addition, the system architecture under the FPGA-based SoC may differ from the real chip. In our previous work, a configurable SoC prototyping platform, namely, CONCORD, was proposed to provide high flexibility, compatibility, and modularity in connection interfaces, for demands from various applications. In this paper, an improved version, named CONCORD II, is proposed. In contrast to CONCORD, CONCORD II operates with higher clock rate, greater FPGA capacity, more types of transmission signals, and additional categories of peripheral sub-modules.
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