In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76[Formula: see text] 170 [Formula: see text]. A total average power range of 60-240 [Formula: see text] for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit.
Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standardcell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far.
A sub-threshold 9-bit adder based on a minority-3 based full adder is designed and analyzed versus technology. A power-delay design space exploration is presented in multiple technology nodes. The performances are demonstrated and compared on spanning technology nodes of 130nm-LP, 65nm-LP-BULK, 28nm-LP-high-k-bulk, 28nm Ultra-Thin-Body-and-BOX (UTFF) FDSOI. An extensive body biasing was then applied to the UTBB FDSOI 28nm technology to adapt the circuit to the target operating frequency of 65MHz. The extensive body biasing exploits the feature provided by the Ultra-Thin-Body-and-BOX Fully Depleted SOI (UTBB FDSOI) technology, which allows a bias range of −300mV ∼3V . The design was implemented in physical level, and all the results account for the layout parasitics. A minimum energy point of 1.03fJ/(bit.cycle) is achieved in the 28nm-UTFF-FDSOI, at the 0.24V supply with the 1.8MHz operating speed. For the target frequency of 65MHz and a 9-bit adder, a total minimum energy operation of 11fJpercycle for a supply voltage of 0.309V and a body voltage of 1.35V is achieved.
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