A Compact 8-Bit AES Crypto-processor

Abstract

Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standardcell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far.

An efficient hardware implementation of SM4

“…Only one data block is in process at any time and the output is returned after 32 clock cycles. Using small data width, reducing the number of S-Box and utilizing lightweight key expansion mechanism were proposed to make AES compact [9][10][11]. AES is a typical block cipher and the method for it can be applied to SM4.…”

“…We call the ultra-compact SM4 design "UCSM4" for short. There are two key expansion mechanisms: one is to pre-compute and store all round keys, and the other is to provide round keys on-the-fly, called on-the-fly key expansion [9]. The former one is applied in most previous works including UCSM4, due to its high performance and low energy consumption when input keys remain the same.…”