A new method for automatic fabrication of a three-dimensional plastic model is presented. A solid model is fabricated by exposing liquid photo-hardening polymer to ultraviolet rays, and stacking the cross-sectional solidified layers. Three types of equipment were constructed, their operational conditions were investigated, and some solid models were fabricated. A transparent plastic model whose internal structure was visible from the outside of the model was obtained. The operations are simple and can be easily automated. The present method is useful in displaying three-dimensional shapes.
A new self-scanned image sensor using a PCD as a scanner is proposed. A 64 bit (MOS type) and a 128 bit (bipolar type) linear photosensor arrays with the PCD scanner were designed and fabricated successfully. The PCD scanner can be operated by such a low clock pulse voltage as 1 to 5 V. Accordingly, a S/N ratio is high because the clock noise from the clock pulse is low. A S/N ratio of more than 35 dB were experimentally obtained without any signal processing. Moreover, the new device proposed here has the advantage of a simple structure and the device with high bit numbers is expected.
A SUB-NS bipolar 8-bit 1600-gate LSI processor fabricated by a Polysilicon Self-Aligned (PSA) method, combined with three-layer metalization and 120-pin gang lead bonding affording high packing density, low power consumption and high speed operation, will be described. An average packing density of 170 gates/mm' has been achieved with .an internal gate of 0.6p.j (0.9ns, 0.67mW) power delay product.with 4 x 5p' (0.16mils x 0.20mils) emitter. The most significant aspect of the PS.4 process, compared with the conventional approach, is that all of the electrodes and the first interconnections are constructed in a poly crystalline silicon layer prior to the formation of emitter-base junctions. As the poly-si electrodes are obtained in a self-aligned fashion with the transistor portions, no additional margin for alignment is required at the contact areas. In addition, these poly-si elements can be patterned to a finer geometry. This characteristic results primarily from the fact that the lateral size of every element in the poly-si laycr is uniformly shrunk by selective thermal oxidation. Further, poly-si high resistance, required especially for a low power LSI, can be fabricated in the poly-si layer at the same stage with the first interconnection construction. Therefore, no area is required for resistors in the transistor array substrate.The PSA process permits three-layer metallization, reducing the wiring area. Currently, Au metallization using an electroplating method is applied for the second and third level interconnections.
A high speed bipolar masterslice LSI has been realized which contains 400 internal gate cells and 60 output gate cells on a 5.7 mm × 5.7 mm chip. Oxide isolation with n-type epiataxial layer and three layer metallization by PMP structure are used for fabrication process. These new technologies afford a large reduction in device size, parasitic capacitance and wiring area, which improve LSI performance. An internal gate is realized by the CML circuit with a 400 mV logic swing and with emitter followers, together with extensive use of emitter-dotting and collector-dotting. Power supply voltage is -3.2 V and output level is compatible with standard ECL. The ALU chip has been fabricated for an application of this masterslice LSI and a 1.48 ns average propagation delay per circuit has been achieved.
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