A high-speed 1600-gate bipolar LSI processor

Abstract

A SUB-NS bipolar 8-bit 1600-gate LSI processor fabricated by a Polysilicon Self-Aligned (PSA) method, combined with three-layer metalization and 120-pin gang lead bonding affording high packing density, low power consumption and high speed operation, will be described. An average packing density of 170 gates/mm' has been achieved with .an internal gate of 0.6p.j (0.9ns, 0.67mW) power delay product.with 4 x 5p' (0.16mils x 0.20mils) emitter. The most significant aspect of the PS.4 process, compared with the conventional approach, is that all of the electrodes and the first interconnections are constructed in a poly crystalline silicon layer prior to the formation of emitter-base junctions. As the poly-si electrodes are obtained in a self-aligned fashion with the transistor portions, no additional margin for alignment is required at the contact areas. In addition, these poly-si elements can be patterned to a finer geometry. This characteristic results primarily from the fact that the lateral size of every element in the poly-si laycr is uniformly shrunk by selective thermal oxidation. Further, poly-si high resistance, required especially for a low power LSI, can be fabricated in the poly-si layer at the same stage with the first interconnection construction. Therefore, no area is required for resistors in the transistor array substrate.The PSA process permits three-layer metallization, reducing the wiring area. Currently, Au metallization using an electroplating method is applied for the second and third level interconnections.