Downscaling of classical metal oxide semiconductor (MOS) devices resulted in a need to replace the gate oxide by high k dielectrics to keep the gate leakage under control. However, new device issues such as an uncontrollable shift in the threshold voltage in p-type MOS devices and a reduction in channel mobility were encountered. These issues can be overcome by the implementation of buried strained SiGe channels, grown by selective epitaxial growth, as demonstrated in this paper. The optimized high k gate fabrication scheme starts with the growth of a very thin oxide layer. Therefore, a Si cap layer is required because oxidation of SiGe leads to defects at the gate/channel interface. The Si growth rate is influenced by the underlying SiGe layer, during the deposition of the first atomic layers. Nevertheless, accurate thickness control of the Si cap is possible. The minimal required Si cap thickness and its dependence on Ge content in the underlying SiGe channel, for making high-quality dielectrics and maintaining low capacitive equivalent thickness, is extracted from charge pumping measurements, CV measurements and energy dispersive x-ray spectroscopy measurements. Device results demonstrate the successful implementation of buried SiGe channels in pMOS devices with high k gate dielectrics.
Device technologies of SiC MOSFETs have nearly matured to the level of mass production and one of the remaining tasks is to serve better solutions in view of both costs and performances for practical systems. Elimination of external reverse diodes in inverter circuits is one of the solutions, by which total area of the SiC chips is greatly reduced leading to lower material cost. A DioMOS (Diode in SiC MOSFET) successfully integrates the reverse diode without any increase of the chip size from the original MOS transistor by utilizing an n-type epitaxial channel under the MOS gate for the reverse conduction path of the diode. The basic concept of the DioMOS has been proposed [1]; meanwhile, further reduction of the on-state resistance together with confirmation of high-speed switching is necessary for its application in power switching systems. In this paper, low on-state resistance (Ron) of 40mΩ and blocking voltage (BVds) of 1700V as well as improved switching performances of DioMOS are demonstrated. The measured results suggest DioMOS to be satisfactory for practical use.
Selective Epitaxial Growth of SiGe and/or Si-cap/SiGe heterostructures offer an elegant way to improve pMOS device performance. This paper discusses some important challenges and characteristics of the corresponding epi process. Loading effects are strongly reduced by choosing the growth conditions away from the mass transport regime, i.e. by reducing the growth pressure and/or increasing the gas velocity. Anomalous SiGe thickening at convex corners of recessed areas and the impact of the underlying SiGe on the growth behavior during Si- capping are discussed as well. The limits of the chemical and thermal budgets during pre-epi treatments as defined by the device concepts require some process optimization but are not a show stopper.
We present the first investigation of low frequency noise in the SiGe channel heterostructure dynamic threshold p-MOSFET (HDTMOS). The sub-threshold characteristics and drain current noises were measured and evaluated. The input referred noise of the SiGe HDTMOS was reduced to about one-tenth compared with that of the Si MOS, because of higher transconductance g, and less interface states at the Si/SiGe hetero-interface.
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