Metal-semiconductor interface is a bottleneck for efficient transport of charge carriers through Transition Metal Dichalcogenide (TMD) based field-effect transistors (FETs). Injection of charge carriers across such interfaces is mostly limited by Schottky barrier at the contacts which must be reduced to achieve highly efficient contacts for carrier injection into the channel. Here we introduce a universal approach involving dry chemistry to enhance atomic orbital interaction between various TMDs (MoS 2 , WS 2 , MoSe 2 and WSe 2 ) & metal contacts has been experimentally demonstrated. Quantum chemistry between TMDs, Chalcogens and metals has been explored using detailed atomistic (DFT & NEGF) simulations, which is then verified using Raman, PL and XPS investigations. Atomistic investigations revealed lower contact resistance due to enhanced orbital interaction and unique physics of charge sharing between constituent atoms in TMDs with introduced Chalcogen atoms which is subsequently validated through experiments. Besides contact engineering, which lowered contact resistance by 72, 86, 1.8, 13 times in MoS 2 , WS 2 , MoSe 2 and WSe 2 respectively, a novel approach to cure / passivate dangling bonds present at the 2D TMD channel surface has been demonstrated. While the contact engineering improved the ON-state performance (I ON , g m , R ON ) of 2D TMD FETs by orders of magnitude, Chalcogen based channel passivation was found to improve gate control (I OFF , SS, & V TH ) significantly. This resulted in an overall performance boost. The engineered TMD FETs were shown to have performance on par with best reported till date.I. Introduction Growth of semiconductor industry is driven by Moore's law 1 which intends to improve the efficiency of electronic gadgets in terms of speed and compactness by 2×, every 1.5 years. This is achieved by aggressive channel length scaling of Silicon MOSFETs. On the other hand, channel length scaling leads to short channel effects (SCE) like drain induced source barrier lowering and threshold voltage roll-off due to compromised gate control over channel. This results into higher source-to-drain leakage current, higher subthreshold slope and lower noise margins, which eventually increases the static power loss across the VLSI system. To mitigate SCE, devices like FinFETs 3, 4, 5 Multi-gate FET 2, 3, 6, 7 , Ultra-thin body (UTB) FETs 6, 8 and Tunnel FETs (TFETs) 9 have been proposed, which offer improved gate control and better SCE immunity. The key in most of the ultrascaled FET concepts is to reduce the channel thickness as the channel length is scaled down. However, scaling channel thickness beyond 5nm leads to mobility degradation and threshold voltage instability due to quantum confinement and surface dangling bonds, which leads to performance roll off. Atomically thin layers of 2D semiconductors like Transition Metal Dichalcogenides (TMDs) 10-15 on the other hand offer better gate control due to lack of dangling bonds perpendicular to their basal plane, as well as missing quantum i...