An inductively coupled contactless dc connector has been proposed for the next-generation 380-V dc distribution system in data centers. A LLC resonant dc-dc converter topology with gallium nitride (GaN) power transistors has been applied to realize the short-distance highly efficient contactless power transfer. A prototype of a 1.2-kW 384-to 192-V connector has been fabricated and the conversion efficiency of over 95% with the power density of 8.1 W/cm 3 has been confirmed experimentally under 1000-kHz operation. The design consideration has been carried out and the potential to achieve 10.0 W/cm 3 has been also shown taking the feature of the GaN power device and the characteristics of the magnetic core material for the transformer into account. The contactless dc connector integrates the functioning of an isolated dc-dc converter into a connector for space saving, and the dc current can be cut off without arc because of the inductive coupling. The proposed connector contributes to realizing a highly efficient, space saving, and reliable future 380-V dc distribution system. Index Terms-Contactless power supply, dc power distribution, dc-dc power converters, gallium nitride (GaN).0093-9994 , he has been with Osaka University.He is engaged in research and development of power converter control in distribution systems and the design methodology for high power density converter using SiC and GaN power devices. Currently, he is mainly engaged in the development of high power density dc power supplies for 380-V dc distribution systems. His research concerns dc power connectors using LLC resonant circuits.Toshifumi Ise was born in 1957. He received the B.Eng., M. Eng., and Doctor of Engineering degrees in electrical engineering
Contactless DC connector has been proposed for high power density 380 V DC power feeding system. A LLC resonant DC-DC converter topology with GaN power transistors and Si-SBDs has been applied to realize high frequency and high efficiency inductively-coupled contactless DC connector. ISOP (input series and output parallel)-IPOS (input parallel and output series) connection topology has been also employed to develop 380 V DC connector. Prototype of a 1.2 kW 384 V-192 V DC connector to constitute a part of 384 V-384 V connector has been fabricated, and maximum efficiency of 96.5% with the ideal power density of 5.4 W/cm 3 has been confirmed experimentally under 500 kHz operation. Design consideration for the proposed connector has been also conducted, and the approach for achieving higher power density of 10 W/cm 3 has been presented.
A contactless DC connector concept has been proposed for next-generation 380-V DC distribution systems in data centers. An LLC resonant DC-DC converter topology with gallium nitride (GaN) power transistors has been applied to realize a highly efficient inductively coupled contactless connector. A prototype of a 1.2-kW 384 V-192 V contactless connector has been fabricated. An efficiency of over 95% and an ideal power density of over 5.0 W/cm 3 have been confirmed experimentally under 500-kHz operation. Design considerations for the proposed connector have been also conducted, and the approach for achieving a higher power density of 10 W/cm 3 has been presented. The proposed concept contributes to realizing a high-power-density DC distribution system because the functions for both the isolated DC-DC converter and conventional connector are integrated in a single instrument.
A 64KBIT DYNAMIC MOS RAR.1, capable of 20011s access time and 150mW power dissipation, has been developed using a single transistor cell and a single-level polysilicon gate process. The 64K RAM is organized as 16-kwords x 4 bits. All clocks, input and output signals are TTL compatible. The number of refresh cycle is chosen to be 128, as in the case of 16K RAMS. Figure 1 shows the block diagram of the 64K RAM, which is drawn on the microphotograph. It includes memory matrix, sense circuits, address buffers, decoders, timing generating circuits and output buffers. The 64K RA31 is divided into four 16K blocks.A sense circuit array is placed in the center of each 16K block to maintain a balanced configuration. Each o f two nodes of a sense circuit is connected to 64 memory cells. Figure 2 shows the sense circuitry which consists of sense circuit, memory cells and two dummy cells. This sense circuit is very sensitive and can detect a signal of less than 2 30mV. Details of this sense circuit have been previously reported'". Dimensions of the single-poly cell are l 4 p m x 15pm. The bit line signal transmitted from a memory cell has been designed t o be f l00mV in the worst case. Therefore, the sense circuit can operate with sufficient margine. The sense circuit is not only very sensitive, but also low power dissipating, 80pW/circuit, due to its dynamic operation.As the MOS FET channel length decreases, VDD a n d v t h become lower and the Vth approaches TTL low lcvcl, so that there is a very small noise margin. The level detecting circuit and its waveform appears in Figure 3. An address buffer, that utilizes the level detecting circuits, has been used in the 64K RAM: Figure 4. It consists of address input. amplification, acceleration and buffer circuits. As the address buffer operates fully dynamically, it dissipates only ImWlcircuit at 500ns cycle time. Moreover, it has TTI, compatibility, in spite of low threshold voltage (0.8V), through adoption of the level dctecting circuit. In the 64K RAM, this level detecting circuit is used not only as an interface circuit to TTL, but frequently as a level detecting circuit within timing generating circuits. Short channel MOS FETs cause a decrease in junction and gate oxide breakdown voltages and punch through voltage and lead to a decrease in de supply voltages and MOS FET threshold voltage. The investigation of delay-power products, concerning short channel MOS FET inverter circuits, was also accomplished, to improve the circuit performance. These restrictions and investigations lead to the adoption of low dc supply voltages; 7V and -2V. Features of the MOS transistor are 2 p m effective __ channel length, 500A gate oxide thickness, 0.25pm junction depth and 0.8V threshold voltage at 1V drain voltage. The 64KRAM has been fabricated utilizing a 2pm-rule VLSI fabrication technology; Figure 1. The measured dependence of access time and power dissipation of the 64K RAM o n VDD are shown in Figure 5 . Key device characteristics of the 64K RAM arc summarized in Table 1. The technol...
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