A 64Kbit MOS RAM

Abstract

A 64KBIT DYNAMIC MOS RAR.1, capable of 20011s access time and 150mW power dissipation, has been developed using a single transistor cell and a single-level polysilicon gate process. The 64K RAM is organized as 16-kwords x 4 bits. All clocks, input and output signals are TTL compatible. The number of refresh cycle is chosen to be 128, as in the case of 16K RAMS. Figure 1 shows the block diagram of the 64K RAM, which is drawn on the microphotograph. It includes memory matrix, sense circuits, address buffers, decoders, timing generating circuits and output buffers. The 64K RA31 is divided into four 16K blocks.A sense circuit array is placed in the center of each 16K block to maintain a balanced configuration. Each o f two nodes of a sense circuit is connected to 64 memory cells. Figure 2 shows the sense circuitry which consists of sense circuit, memory cells and two dummy cells. This sense circuit is very sensitive and can detect a signal of less than 2 30mV. Details of this sense circuit have been previously reported'". Dimensions of the single-poly cell are l 4 p m x 15pm. The bit line signal transmitted from a memory cell has been designed t o be f l00mV in the worst case. Therefore, the sense circuit can operate with sufficient margine. The sense circuit is not only very sensitive, but also low power dissipating, 80pW/circuit, due to its dynamic operation.As the MOS FET channel length decreases, VDD a n d v t h become lower and the Vth approaches TTL low lcvcl, so that there is a very small noise margin. The level detecting circuit and its waveform appears in Figure 3. An address buffer, that utilizes the level detecting circuits, has been used in the 64K RAM: Figure 4. It consists of address input. amplification, acceleration and buffer circuits. As the address buffer operates fully dynamically, it dissipates only ImWlcircuit at 500ns cycle time. Moreover, it has TTI, compatibility, in spite of low threshold voltage (0.8V), through adoption of the level dctecting circuit. In the 64K RAM, this level detecting circuit is used not only as an interface circuit to TTL, but frequently as a level detecting circuit within timing generating circuits. Short channel MOS FETs cause a decrease in junction and gate oxide breakdown voltages and punch through voltage and lead to a decrease in de supply voltages and MOS FET threshold voltage. The investigation of delay-power products, concerning short channel MOS FET inverter circuits, was also accomplished, to improve the circuit performance. These restrictions and investigations lead to the adoption of low dc supply voltages; 7V and -2V. Features of the MOS transistor are 2 p m effective __ channel length, 500A gate oxide thickness, 0.25pm junction depth and 0.8V threshold voltage at 1V drain voltage. The 64KRAM has been fabricated utilizing a 2pm-rule VLSI fabrication technology; Figure 1. The measured dependence of access time and power dissipation of the 64K RAM o n VDD are shown in Figure 5 . Key device characteristics of the 64K RAM arc summarized in Table 1. The technol...

Circuit design of large scale dynamic MOS RAM with scaling relationships

“…However, f o r s i m p l i c i t y it can be found a n a l y t i c a l l y using t h e b a s i c MOST character- The c o e f f i c i e n t rn denotes t h e r a t i o of AVR t o d r~~~~~ as given by (1) and ( 2 ) The second cause can be l i m i t e d t o a c e r t a i n e x t e n t by fabr i c a t i o n c o n d i t i o n s and t h e t h i r d can be improved by c a r e f u l lay-out.…”

“…I n p a r t i c u l a r , i n conjunction with EB exposure techniques, p a t t e r n d e f i n i t i o n has been f u r t h e r r e f i n e d and the packaging density of information processing devices has r i s e n i n recent years. To decrease c o s t s i n large-scale RAM developments, t h e number of b i t s per chip has doubled annually and technological 82 progress, although slowed s l i g h t l y , s t i l l continued [1]- [3]. Further i n t e g r a b i l i t y of large-scale RAM must r e l y e n t i r e l y on improvements i n fabr i c a t i o n and i n device and c i r c u i t techniques.…”