A 64KBIT DYNAMIC MOS RAR.1, capable of 20011s access time and 150mW power dissipation, has been developed using a single transistor cell and a single-level polysilicon gate process. The 64K RAM is organized as 16-kwords x 4 bits. All clocks, input and output signals are TTL compatible. The number of refresh cycle is chosen to be 128, as in the case of 16K RAMS. Figure 1 shows the block diagram of the 64K RAM, which is drawn on the microphotograph. It includes memory matrix, sense circuits, address buffers, de…
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