Circuit design of large scale dynamic MOS RAM with scaling relationships

Abstract

Further integration of the dynamic MOS RAM (MOS(D)RAM) depends on improvements in fabrication and in device and circuit techniques. To attain better operating characteristics and stable operation for large‐scale integration, it is necessary to establish a design approach that combines all of these techniques. This paper describes such an approach. First, the coefficient m defining the sensitivity, read‐voltage and the operating region of the sense circuit is established and the design guidelines of the sense circuit are then derived. Analysis of the coefficient m shows that variations in device parameters attributable to processing accuracy significantly affect the stability of the large‐scale MOS(D)RAM operation. To obtain a wide operating region for the 64K MOS(D)RAM, the 128 refresh method is shown to be advantageous. Next, based on the design guidelines it is shown experimentally that 64KMOS(D)RAM can be fabricated with wide upper‐ and lower‐operating limits and that the design approach to large‐scale MOS(D)RAM using the fine‐pattern fabrication technique presented here is indeed valid.