Increasing capacitance density could be achieved by mainly two methods: increasing the capacitor node area and adopting higher dielectric constant (κ) material. The former relates mostly to integration issues, such as deep capacitor hole etching with an aspect ratio over 50 and filling the hole with the conformal electrode material. The latter is mainly a material issue, requiring appropriate material selection and an extremely conformal film deposition process. It also must be compatible with the electrode material, which means no adverse interfacial reaction and phase-pure high-κ film growth.Given the industry-compatible and matured electrode fabrication process of TiN grown by the atomic layer deposition (ALD) process, ZrO 2 has been the leading high-κ material in DRAM fabrication. This is because the crystalline structure of the thin-film ZrO 2 transforms from the medium-κ (≈20) monoclinic phase to the high-κ (>≈40) tetragonal phase due to the surface-energy effect. [6,7] Also, the ALD process of ZrO 2 is well matured to secure mass production. However, undoped ZrO 2 has suffered from a high leakage current problem. The problem could be ascribed to the local current flow through the grain boundaries of the polycrystalline ZrO 2 [8] and the n-type nature (the Fermi level is close to the conduction band edge) of the material by the presence of oxygen vacancies. [9,10] This problem has been overcome by adopting a thin Al 2 O 3 insertion layer (IL) for the relatively thicker ZrO 2 or doping the ZrO 2 with Al for thinner films. [8][9][10][11][12] However, such a strategy has sacrificed capacitance density owing to the inclusion of the lowκ amorphous Al 2 O 3 layer (κ ∼ 6-9) or the degraded crystallinity of the Al-doped ZrO 2 . [10,13,14] Therefore, the DRAM industry has spent the enormous effort to optimize the dielectric stack structure, but it has become evident that next-generation dielectric material is necessary for further scaling.Among the diverse candidates with even higher κ-values, SrTiO 3 showed a severe incompatibility with the TiN electrode. [15,16] Hf-doping into the ZrO 2 could be a viable and immediate option, but it involves a risk of loss of discharging density and slow operation speed. This problem is owing to the possible involvement of the (anti-) ferroelectric effect of the Hf-doped This study examines the influences of the Al 2 O 3 and Y 2 O 3 insertion layers (ILs) on the structural and electrical features of ZrO 2 thin films for their application to dynamic random access memory capacitors. The ultra-thin Al 2 O 3 IL (0.1-0.2 nm) dissolves into the ZrO 2 layers, which causes the top and bottom portions of the ZrO 2 film to merge and have smaller lattice parameters. However, the thicker Al 2 O 3 IL (>≈0.4 nm) forms a continuous layer and separates the top and bottom portions of the ZrO 2 film. Interestingly, the diffusion of Al does not occur in this case. Overall, the dielectric constant (κ) of the ZrO 2 /Al 2 O 3 /ZrO 2 film is lower than that of the undoped ZrO 2 film due to the involveme...
Ruthenium (Ru) thin films deposited via atomic layer deposition (ALD) with a normal sequence and discrete feeding method (DFM) and their performance as a bottom electrode of dynamic random-access memory (DRAM) capacitors were compared. The DFM-ALD was performed by dividing the Ru feeding and purge steps of the conventional ALD process into four steps (shorter feeding time + purge time). The surface morphology of the Ru films was improved significantly with the DFM-ALD, and the preferred orientation of the Ru films was changed from relatively random to a <101>-oriented direction. Under the DFM-ALD condition, the higher susceptibility of oxygen atoms to the Ru electrode resulted in a higher proportion of the RuO2 formation on the Ru film surface during the subsequent TiO2 ALD process. This higher RuO2 portion leads to higher crystallinity of the local-epitaxially grown TiO2 films with a rutile phase. Such improvement also decreased the interfacial component of equivalent oxide thickness (EOTi) by ∼0.1 nm compared with the cases on sputtered Ru film, which showed an even smoother surface morphology. Consequently, the minimum EOT values when the Ru bottom electrodes deposited via DFM-ALD were adopted were 0.76 and 0.48 nm for TiO2 and Al-doped TiO2 films, respectively, while still satisfying the DRAM leakage current density specification (<10–7 A/cm2 at a capacitor voltage of 0.8 V).
To improve the water-resistance of the MgO-based metal-insulator-metal (MIM) capacitors, BeO/MgO/BeO/MgO/BeO (BMBMB) stacked layers with a total thickness of ~ 10 nm (2/2/2/2/2 nm) were deposited at 335°C by atomic...
For Ge‐based metal‐oxide‐semiconductor field‐effect transistor application, high‐k Y2O3 thin films are deposited on Ge single‐crystal substrate using atomic layer deposition. The primary drawbacks of a metal‐oxide‐semiconductor capacitor with pristine Y2O3 are large hysteresis and high leakage current. Through forming gas annealing (FGA), the leakage current can be reduced by approximately three orders of magnitude, along with the reduction of interface trap density. However, there is still a large hysteresis in the capacitance–voltage curves. O3 post‐deposition annealing (OPA) is used to solve the problem. The formation of the YGeOx interfacial layer through OPA and the reduction of the defect level of the Y2O3 thin film effectively decrease the hysteresis, which also decreases the leakage current. Additionally, the hysteresis is 690 mV when only FGA is performed. However, it is further reduced to 260 mV through OPA. Moreover, the remote oxygen scavenging effect using TiN/Pt electrodes prevents an unintentional increase in equivalent oxide thickness (EOT). The 4.7 nm thick Y2O3 film results in an EOT of 1.77 nm and leakage current density of 2.1 × 10−7 A cm−2 (at flat band voltage—1 V) after the OPA.
Y2O3/TiO2 bilayer thin films and Y-doped TiO2 (YTO) thin films were deposited on a Ge substrate by atomic layer deposition at a substrate temperature of 250 °C. They were used as gate insulators to examine the electrical properties of Pt/TiN/TiO2/Y2O3/p-Ge and Pt/TiN/YTO/p-Ge metal–oxide–semiconductor capacitors. A 7 nm thick bilayer thin film showed a lower leakage current density by more than one order of magnitude compared to a YTO thin film with the same thickness due to the high conduction band offset between the Y2O3 layer and Ge substrate. However, the bilayer thin film showed a large hysteresis of 950 mV. On the other hand, the YTO thin film showed significantly reduced hysteresis of 120 mV due to the smaller slow trap density. The voltage acceleration factors of the bilayer thin film and YTO thin film were 1.12 and 1.25, respectively, higher in the YTO thin film. The interfacial trap density of the 7 nm thick bilayer and YTO thin films were 3.5 × 1011 cm−2 eV−1 and 2.7 × 1011cm−2 eV−1, respectively. The equivalent oxide thickness of the YTO film could be scaled down to 0.9 nm, and a leakage current density of 1.4 × 10−4A cm−2 at flat band voltage −1 V was achieved. This study confirmed that the YTO film can be used as a promising ternary high-k oxide for a Ge-based field-effect-transistor.
In this study, an Al 2 O 3 capping layer (ACL) was utilized to enhance the surface morphology and electrical properties of SrRuO 3 (SRO) electrode films deposited via combined atomic layer deposition and pulsed chemical vapor deposition. To crystallize the SRO films, postdeposition annealing (PDA) was necessary; however, this led to material agglomeration and degradation of the surface morphology. Therefore, to address this issue, the ACL was used to reduce agglomeration by inhibiting material migration. Next, the appropriate thickness of ACL and PDA conditions, which ensured high crystallinity and suppressed agglomeration, were investigated. Subsequently, the ACL was wetetched using an aqueous HF solution. The changes in the layer density of Ru and Sr were analyzed, and the stoichiometric SRO film was stably obtained after PDA and wet-etching. The resulting ACL-etched SRO film had an improved surface morphology, lower resistivity (∼800 μΩ•cm), and lower root-mean-squared roughness (1.15 nm) compared to uncapped SRO films at a thickness of 25 nm. Finally, the atomic layer-deposited SrTiO 3 dielectric layer on the SRO film was in situ-crystallized, with a high dielectric constant of 81 and a minimal interfacial equivalent oxide thickness of 0.03 nm.
The physicochemical and electrical properties of Pt/Al-doped TiO2 (ATO)/Ru/TiN capacitors were investigated by adopting an atomic-layer-deposited Ru interlayer between the ATO and the TiN layers. The Ru interlayer induced local-epitaxial growth of the ATO films to the rutile phase, resulting in improved electrical properties. The work function and surface morphology of the Ru/TiN bottom electrode affected the electrical properties of the capacitors. When the Ru interlayer was too thin (<1.5 nm) to completely cover the entire TiN surface, a mixture of rutile/anatase/amorphous ATO dielectric films was grown, resulting in negligible improvement in the electrical properties. With an increased Ru interlayer thickness, the work function of the bottom electrode increased and the crystallinity of the rutile ATO film was improved. However, when the Ru interlayer was too thick, the capacitors became degraded because of the rough surface morphologies of the electrode and dielectric films. Consequently, the improvement of the electrical performances was maximized with a Ru interlayer thickness of ∼2.5 nm. The achieved minimum equivalent oxide thickness (EOT) was ∼0.52 nm with a low leakage current density (<10–7 A/cm2 at a capacitor voltage of 0.8 V). This performance was comparable to that of a bulk Ru bottom electrode.
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