This paper proposes a high‐speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross‐connect system. The proposed switch architecture, named the high‐speed‐retry banyan switch, employs a bufferless banyan network between input and output buffers; a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell‐retransmission algorithm, is employed as is a ring‐arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless highspeed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high‐speed‐retry banyan switch. The prototype system, even in its present state, could be used to realize a giga‐bit‐rate BISDN switching system.
In the design of concentration and distribution stages of analog video signal systems, the use of broadband analog switches helps to reduce the number of expensive bandwidth-reduction CODECs. However, these switches must satisfy severe crosstalk attenuation requirements. To suppress the crosstalk, switch components and packaging must be chosen carefully and switch configurations and their implementation must also be considered. Moreover, the conventional design for one-to-one crosstalk cannot be applied to adistribution service for video signals, and a more detailed design that considers crosstalk phase conditions is required. However, no method of allocating the crosstalk attenuation objective to each component in the switch has yet been established for connecting one inlet to multiple outlets .This paper presents a model for crosstalk addition based on the generation mechanism of crosstalk and proposes the concept of equivalent power sum multiplicity. Using this model and concept, a method is proposed of allocating a crosstalk attenuation objective to each cornponent of the switch in order to satisfy the overall quality.
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