A high‐speed‐retry banyan switch architecture for giga‐bit‐rate BISDN networks

Abstract

This paper proposes a high‐speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross‐connect system. The proposed switch architecture, named the high‐speed‐retry banyan switch, employs a bufferless banyan network between input and output buffers; a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell‐retransmission algorithm, is employed as is a ring‐arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless highspeed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high‐speed‐retry banyan switch. The prototype system, even in its present state, could be used to realize a giga‐bit‐rate BISDN switching system.