Power is a big problem in data centers and a significant fraction of this power is consumed by the storage system. Server storage systems use a large number of disks to achieve high performance, which increases their power consumption. In this paper, we propose to significantly reduce the power consumed by the storage system via intra-disk parallelism, wherein disk drives can exploit parallelism in the I/O request stream. Intra-disk parallelism can facilitate replacing a large disk array with a smaller one, using the minimum number of disk drives needed to satisfy the capacity requirements. We show that the design space of intra-disk parallelism is large and present a taxonomy to formulate specific implementations within this space. Using a set of commercial workloads, we perform a limit study to identify the key performance bottlenecks that arise when we replace a storage array that is tuned to provide high performance with a single high-capacity disk drive. These are the bottlenecks that intra-disk parallelism would need to alleviate. We then explore a particular intra-disk parallelism approach, where a disk is equipped with multiple arm assemblies that can be independently controlled, and evaluate three disk drive designs that embody this form of parallelism. We show that it is possible to match, and even surpass, the performance of a storage array for these workloads by using a single disk drive of sufficient capacity that exploits intra-disk parallelism, while significantly reducing the power consumed by the storage system compared to the multi-disk configuration. We evaluate the performance and power consumption of disk arrays composed of intra-disk parallel drives, discuss the engineering issues involved in implementing such drives, and finally provide a preliminary cost-benefit analysis of building and deploying intra-disk parallel drives, using cost data obtained from several companies in the disk drive industry.
Abstract-There is growing interest in emerging non-volatile memory technologies such as Phase-Change Memory, Memristors, and Spin-Transfer Torque RAM (STT-RAM). STT-RAM, in particular, is experiencing rapid development that can be difficult for memory systems researchers to take advantage of. What is needed are techniques that enable designers to explore the potential of recent STT-RAM designs and adjust the performance without needing a detailed understanding of the physics. In this paper, we present the STeTSiMS STT-RAM Simulation and Modeling System to assist memory systems researchers.After providing background on the operation of STT-RAM magnetic tunnel junctions (MTJs), we demonstrate how to fit three different published MTJ models to our model and normalize their characteristics with respect to common metrics. The high-speed switching behavior of the designs is evaluated using macromagnetic simulations. We have also added a first-order model for STT-RAM memory arrays to the CACTI memory modeling tool, which we then use to evaluate the performance, energy consumption, and area for: (i) a high-performance cache, (ii) a high-capacity cache, and (iii) a high-density memory.
Abstract-Flash memory is widely used in consumer electronics products, such as cell-phones and music players, and is increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even servers. There is a rich microarchitectural design space for flash memory and there are several architectural options for incorporating flash into the memory hierarchy. Exploring this design space requires detailed insights into the power characteristics of flash memory. In this paper, we present FlashPower, a detailed analytical power model for Single-Level Cell (SLC) based NAND flash memory, which is used in high-performance flash products. We have integrated FlashPower with CACTI 5.3, which is widely used in the architecture community for studying memory organizations. FlashPower takes as input device technology and microarchitectural parameters to estimate the power consumed by a flash chip during its various operating modes. We have validated FlashPower against published chip power measurements and show that they are comparable. I. INTRODUCTIONFlash is the most popular solid-state memory technology used today. Flash memory is widely used in consumer electronics products, such as cell-phones and portable music players, and flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the storage of choice in laptops, desktops, and even servers. While most research on flash has focused on the device technology and the circuit-level design of flash chips [2], or on high-level system issues such as file-system and Flash-Translation Layer design [4], there has been growing interest in the computer architecture community on flash memory. Computer architects have begun exploring a variety of topics related to flash, including the design of SSDs [3], disk-caches [8], and even new flash-based server architectures [1]. In order to study this architecture design space, architects require simulation tools that can provide detailed insights into the behavior of different flash memory organizations. In particular, a tool that provides an accurate estimate of the power consumed by various flash memory organizations is necessary. To the best of our knowledge, there is no such publicly available tool.In this paper, we present FlashPower, a detailed analytical power model for Single-Level Cell (SLC) NAND flash memory chips, which are used in high-performance flash-based architectures. FlashPower models the key components of a flash chip during the read, program, and erase operations and when idle and is parameterized to facilitate the exploration of a wide spectrum of flash memory organizations. We have integrated FlashPower with CACTI 5.3 [17], which is a widely used tool in the architecture community for studying memory organizations, and is suitable for use in conjunction with an architecture simulator. We validate FlashPower against published chip power measurements [5] and show that the
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