Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)

Nigam,; Smullen,; Mohan, .; Chen, Guihai; Gurumurthi,; Stan, Mircea R.

doi:10.1109/islped.2011.5993623

Cited by 87 publications

(38 citation statements)

References 15 publications

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“…While Chatterjee et al [7] studied the failure rate of a single STT-RAM cell using basic models for transistor and MTJ resistance, process variation effects such as RDF and geometric variation were considered in [15,28]. In this section, we also present the effects of process variation and geometric variation.…”

Section: Errors In Read and Write Operationsmentioning

confidence: 99%

“…There are several factors that affect the failure in STT-RAM memories: access transistor manufacturing errors such as those due to RDFs, channel length, and width modulations, geometric variations in MTJ such as area and thickness variation, and thermal fluctuations that are modeled by the initial magnetization angle variation [15]. Note that all these variations cause hard errors.…”

Section: Stt-ram Error Modelmentioning

confidence: 99%

“…This threshold value can be adjusted using circuit-level techniques to reduce bit error rate (BER) to 10 -4 . The source of errors in STT-RAM is quite different from that of PRAM [13][14][15]. Majority of the errors are due to process variations [13,15].…”

Section: Introductionmentioning

confidence: 99%

“…The source of errors in STT-RAM is quite different from that of PRAM [13][14][15]. Majority of the errors are due to process variations [13,15]. These include variation of the access transistor sizes (W/L), variation in V th due to random dopant fluctuation (RDF), MTJ geometric variation and thermal fluctuations that are modeled using change in initial magnetization angle of the MTJ [15].…”

Section: Introductionmentioning

confidence: 99%

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Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Yang

Emre

Cao

et al. 2012

EURASIP J. Adv. Signal Process.

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Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10 -8 . For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10 -8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

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Section: Errors In Read and Write Operationsmentioning

confidence: 99%

Section: Stt-ram Error Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Yang

Emre

Cao

et al. 2012

EURASIP J. Adv. Signal Process.

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“…Interestingly, solving these differential equations is equivalent to solving for the voltage of a charging capacitor connected with the appropriate time varying current source ( Fig. 2.3) [15,16]. This analogous behavior allows the LLG equations to be represented as a circuit which HSPICE can solve.…”

Section: Macrospin Modelmentioning

confidence: 99%

Modeling of Spintronic Devices: From Theory to Applications

Kabir

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In recent years, there has been a paradigm shift ushered in by More-than-Moore technologies which has focused on functional diversification of modern circuits rather than geometric scaling. One of the promising technologies in this field has been spintronics devices which exploits the spin of an electron instead of its charge. Furthermore, the integration of magnetic spintronics devices with MOSFET circuits-demonstrated by commercial devices such as STT-MRAM-has opened the possibility of Systems-on-Chip (SoC) integrated circuits with both types of components.While there are many physics-based simulators which can study the detailed dynamics of magnetic materials and many CAD tools for large scale circuit design, there is a dearth of simulation tools for circuit designers working with spintronics devices. This dissertation proposes a Verilog-A behavioral hardware model of multiferroic and spin transfer torque (STT) devices which can be incorporated within traditional large scale CAD tools such as Synopsys HSPICE. Using this simulation platform, this work explores how spintronics devices can implement several More-than-Moore applications and proposes circuit and architecture-level designs to realize those applications. This dissertation considers two promising developments in magnetic spintronics devices-logic using multiferroic materials and applications using ii Abstract iii spin-torque nano-oscillators (STNO).Multiferroic materials describe a class of materials which exhibit both ferroelectric and ferromagnetic behaviors. The combination of these two attributes allows for the control of the magnetic state of the material using an electric field rather than a magnetic fielda process known as electrically assisted magnetic switching (EAMS). This work develops a Verilog-A model which captures the EAMS process in multiferroic materials through a compact thermodynamic model. This model demonstrates that multiferroic nanopillars can not only be used to represent binary logic bits, but they also provide a third state that can be used for reconfiguration similar to traditional field programmable gate arrays (FPGAs). This dissertation describes the operations of a reconfigurable array of magnetic automata (RAMA) based on multiferroic nanopillars which can perform ultra-low power computation.Yet another method to control the magnetization of materials using electrical currents is through the spin transfer torque (STT) effect. The STT effect manifests in magnetic tunnel junctions (MTJ) when a DC current is applied through the junctions. The modularity of the proposed Verilog-A model can be modified to include the STT effect to simulate the behavior of spin torque nano-oscillators. Furthermore, this model shows that connecting multiple STNOs leads to complex behaviors such as synchronization. In an array of parallel-connected STNOs, this synchronization can be exploited for pattern recognition applications. Finally, this dissertation explores applications using STNOs as on-chip RF components such as bandpass and ba...

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