Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

Abstract

Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10 -8 . For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10 -8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches

“…The Bose-Chaudhuir-Hocquenghem (BCH) code for STT-MRAM was investigated in [22]. In [12], Floating-ECC architec- and BCH product codes were utilized [22], and while they provide superior performance, they need more complexity. This additional complexity is undesirable for cache memory, which requires fast read and write rates.…”

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities

“…In STT-MRAM memories, stored 1's are more vulnerable to write and retention errors than stored 0's. The resulting error rate difference may reach 3 orders of magnitude [3] [8].…”

“…According to (8), in the presence of selective code word inversion, the maximum (worst-case) number of vulnerable values per code word increases linearly with s i.e. the number of even check-bits.…”

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

“…Nevertheless, they suffer from poor reliability that manifests in the form of low manufacturing yield, as well as run-time errors. Furthermore, ensuring high reliability through design leads to increased read and write energy and reduced density [Wu et al, 2009;Zhou et al, 2009;Xu et al, 2009;Del Bel et al, 2014;Kang et al, 2013;Yang et al, 2012].…”