Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Abstract

Spin-Transfer Torque MRAMs are attractive due to their non-volatility, high density and zero leakage. However, STT-MRAMs suffer from poor reliability due to shared read and write paths. Additionally, conflicting requirements for data retention and write-ability (both related to the energy barrier height of the storage device) makes design more challenging. Furthermore, the energy barrier height depends on the geometry of the storage. Any variations in the geometry of the storage device lead to variations in the energy barrier height. In order to address poor reliability of STT-MRAMs, usage of Error Correcting Codes (ECC) has been proposed. Unlike traditional CMOS memory technologies, ECC is expected to correct both soft and hard errors in STT-MRAMs. To achieve acceptable yield with low write power, stronger ECC is required, resulting in increased number of encoded bits and degraded memory capacity. In this paper, we propose Failure-aware ECC (FaECC), which masks permanent faults while maintaining the same correction capability for soft errors without increased number of encoded bits. Furthermore, we investigate the impact of process variations on run-time reliability of STT-MRAMs. In order to analyze the effectiveness of our methodology, we developed a cross-layer simulation framework that consists of device, circuit and array level analysis of STT-MRAM memory arrays. Our results show that using FaECC relaxes the requirements on the energy barrier height, which reduces the write energy and results in smaller access transistor size and memory array area.

A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches

“…Several techniques have been presented in the literature to overcome each source of errors in STT-MRAM memories. Increasing write current and write pulse width, decreasing the thermal stability factor, reading and verifying data after each write (write-read-verify), and employing 𝐸𝑟𝑟𝑜𝑟-𝐶𝑜𝑟𝑟𝑒𝑐𝑡𝑖𝑛𝑔 𝐶𝑜𝑑𝑒𝑠 (ECCs) are the technique to overcome the write failures [23], [42], [45], [46], [49]- [53]. Reducing read current and read pulse width, increasing thermal stability factor, overwriting after each read, and employing ECCs are among the techniques that tackle read disturbance [19], [38], [43], [44], [54].…”

“…A 𝑤𝑟𝑖𝑡𝑒 𝑓 𝑎𝑖𝑙𝑢𝑟𝑒 occurs when the content of a cell is not switched by the current applied during the write operation. The origin of all these errors is the stochastic switching behavior of STT-MRAM cells [39], [42]- [44].…”

“…Where, 𝜏 is attempt period equal to 1ns, I 𝑟 𝑒𝑎𝑑 is read current, 𝐼 𝐶 0 is critical switching current, t 𝑟 𝑒𝑎𝑑 is read pulse duration, and Δ is thermal stability factor. Write failure as another reliability challenge occurs when the magnetic field direction of the free layer in MTJ cannot be switched during the interval where write pulse is applied [39], [42]. The MTJ switching time depends on various parameters, e.g., MTJ switching current, process variations, thermal fluctuations, and switching pulse width.…”

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches

“…As depicted, read disturbance rate exponentially increases by ∆ reduction; and, ∆ reduces by increasing the temperature, as mentioned earlier. The occurrence probability of a write failure for a STT-MRAM cell is shown in (5) [42], [43].…”