FlashPower: A detailed power model for NAND flash memory

Abstract

Abstract-Flash memory is widely used in consumer electronics products, such as cell-phones and music players, and is increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even servers. There is a rich microarchitectural design space for flash memory and there are several architectural options for incorporating flash into the memory hierarchy. Exploring this design space requires detailed insights into the power characteristics of flash memory. In this paper, we present FlashPower, a detailed analytical power model for Single-Level Cell (SLC) based NAND flash memory, which is used in high-performance flash products. We have integrated FlashPower with CACTI 5.3, which is widely used in the architecture community for studying memory organizations. FlashPower takes as input device technology and microarchitectural parameters to estimate the power consumed by a flash chip during its various operating modes. We have validated FlashPower against published chip power measurements and show that they are comparable. I. INTRODUCTIONFlash is the most popular solid-state memory technology used today. Flash memory is widely used in consumer electronics products, such as cell-phones and portable music players, and flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the storage of choice in laptops, desktops, and even servers. While most research on flash has focused on the device technology and the circuit-level design of flash chips [2], or on high-level system issues such as file-system and Flash-Translation Layer design [4], there has been growing interest in the computer architecture community on flash memory. Computer architects have begun exploring a variety of topics related to flash, including the design of SSDs [3], disk-caches [8], and even new flash-based server architectures [1]. In order to study this architecture design space, architects require simulation tools that can provide detailed insights into the behavior of different flash memory organizations. In particular, a tool that provides an accurate estimate of the power consumed by various flash memory organizations is necessary. To the best of our knowledge, there is no such publicly available tool.In this paper, we present FlashPower, a detailed analytical power model for Single-Level Cell (SLC) NAND flash memory chips, which are used in high-performance flash-based architectures. FlashPower models the key components of a flash chip during the read, program, and erase operations and when idle and is parameterized to facilitate the exploration of a wide spectrum of flash memory organizations. We have integrated FlashPower with CACTI 5.3 [17], which is a widely used tool in the architecture community for studying memory organizations, and is suitable for use in conjunction with an architecture simulator. We validate FlashPower against published chip power measurements [5] and show that the

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