An 85[Formula: see text]GHz buffer with high power gain is shown in this paper. In order to obtain high power gain, two classic techniques to improve power gain are adopted. The first one is cascade structure of two power stages, and the other one is that each stage utilizes differential cascode structure. Meanwhile, the step-by-step pre-matching technique is applied to optimize the performance of buffer. The stability factor and output power are both improved with other critical design strategies, and a tradeoff is made between gain and efficiency. What’s more, single-ended transformer matching network (TMN) is applied to simplify matching method. The simplified matching method is easy to use with smith chart and works very well, then a modified transformer model is adopted to analyze and optimize the performance of TMN with iterations of impedance matching. After fabricated by 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology, the buffer shows 18.5[Formula: see text]dB power gain and 2[Formula: see text]dBm output power of 1[Formula: see text]dB gain compression point with 2.8[Formula: see text]V supply voltage and 40[Formula: see text]mA operating current, and the saturated output power is 6.33[Formula: see text]dBm.
This Letter presents a 0.35-1.5 GHz 5 × 5 switch matrix chip with a chessboard structure. In the proposed structure, by reassigning the position and switch mode of 25 passive switch grids which almost consume no DC power, the switch matrix can choose and transmit any eight of 16 input signals to the output ports on four directions at the same time. Throughput and the expansion ability of the switch matrix are markedly improved by flexibly choosing a signal path and reusing the switch grids. Besides, wideband gain compensation circuit modules and gain equalisers are used to compensate for insertion loss and gain flatness of the switch matrix. Fabricated by 0.18 μm SiGe BiCMOS technology, the measured highest insertion gain of a signal path is 10 dB. Meanwhile, insertion gains of all signal paths are higher than −6 dB, and isolations of all signal paths are better than 40 dB.
This paper presents an amplifier-douler chain to double the signal frequency from 21GHz to 42GHz with about 10GHz bandwidth of output frequency. For the improvement of conversion gain, the doubler adopts the fully differential Gilbert structure which provides large bandwidth and high conversion gain. Meanwhile, an inductive series LC network is used to form resonant tank with the parasitic capacitor to suppress the second harmonic of input frequency, hence the conversion gain of doubler is improved. Once again, the RLC parallel resonant network is employed as load of doubler and power amplifier, and it can improve bandwidth and conversion gain, too. What's more, transformer matching networks (TMN) are adopted to optimize the bandwidth and conversion gain of amplifier-douler chain. Finally, the amplifier-douler chain which fabricated by IBM SiGe 0.13μm BiCMOS technology shows 6.1dB conversion gain and -4.1dBm saturation output power with 26.5mA operating current and 2.8V supply voltage, and the fundamental and 3 rd harmonic rejection at 42GHz are 17.5dB and 38.6dB, respectively.
Abstract-A single stage 900 MHz power amplifier (PA) with linearization bias circuit is designed with HHNEC 0.5 µm BIS500G power SiGe BiCMOS process. It is implemented by single-ended common emitter structure as a class AB power amplifier. The adopted active bias circuit is originally explained by using two virtue current sources, so that the mechanism of the improvement of linearity can be described more clearly. Then the mechanism is applied to guide the design of a power amplifier with an active bias circuit, which shows better linearity than resistor biased power amplifier by simulation. Through further design and measurement, the fabricated single stage power amplifier exhibits output power 1 dB compression point (OP1 dB) of 18.9 dBm, with power added efficiency (PAE) of 26.75% and power gain of 20.9 dB under 3.3 V voltage supply.
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