The demand for high speed, low power and small chip area with considerable noise immunity have become the need of this modern era with technology scaling down to sub nanometer range. In this paper we have presented the analysis and comparison of our proposed domino design with other classic and noise immune domino designs. Power delay product of the proposed style is 10% less than the footed Domino technique, while 23% less compared to PS technique, while the proposed technique shows a reduction of 22% in Area delay product.
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