Design and synthesis of dynamic circuits

Characterization of logic circuit techniques for high leakage CMOS technologies

“…We first begin with a unate nonmonotonic static circuit in (a) that is assumed to have been optimized but with two trapped inverters. Example unate mapping algorithms can be found in [14,22]. Other assumptions are that all inputs (a-j) are freely available, including their complements, and ideal latches force inputs high or low to provide the correct signals during evaluation and reset.…”

“…Synopsys Design Compiler was used to create the initial unate non-monotonic circuit using 2-input AND gates, 2-input OR gates, and inverters. Using a similar algorithm as in [14], the circuit was then mapped to static NAND, NOR, and inverter gates as shown in Figure 9(a). Following the above example, each level of logic was made successively monotonic.…”

“…This advantage arises, however, from the necessary monotonic property of the logic synthesis, and not from the dynamic nature of the circuit. Static logic can also avoid particularly leaky static paths if it has a similar monotonic property and a reset capability [14]. In addition, monotonicity can potentially reduce dynamic power by eliminating glitching.…”

“…a trapped inversion), logic duplication is necessary to remove the inversion and provide both signal polarities with the same type. Logic duplication will at most double the amount of original logic while maintaining the same logic depth [14,15].…”

Self-resetting stage logic pipelines

“…Recently, other efforts began to focus on designing circuit logic families such as dynamic CMOS that are better suited to support lowpower fast asynchronous logic. However, few tools are available to synthesize and verify large size architectures implemented in these circuit families [1]. At the most, these efforts show proof of concepts using small data path modules without providing any insight on how they would perform in the context of a large architecture.…”