Domino logic synthesis using complex static gates

Abstract

The demand for high speed, low power and small chip area with considerable noise immunity have become the need of this modern era with technology scaling down to sub nanometer range. In this paper we have presented the analysis and comparison of our proposed domino design with other classic and noise immune domino designs. Power delay product of the proposed style is 10% less than the footed Domino technique, while 23% less compared to PS technique, while the proposed technique shows a reduction of 22% in Area delay product.

Monotonic static CMOS and dual-VT technology

“…Our approach uses a concurrent two-coloring and technology mapping algorithm [9] to merge a unate network's non-inverting functions into an alternating pattern of LS and HS gates. There are two ways to implement a non-inverting function.…”

“…However, logic gates in a monotonic static CMOS network can be skewed to favor a certain direction because each gate is guaranteed to exclusively make only a pull-up or a pull-down transition in a clock cycle. This is done by alternating low-skewed and high-skewed static gates such that every other gate output in a path is monotonically rising or monotonically falling [9]. In order for a gate's output to monotonically rise or fall, the concept of a precharge and evaluation time for the logic network is needed.…”

“…During the evaluation phase of clk, the output of the LS (HS) gate will either switch from 1 to 0 (0 to 1) or remain at the precharged value. A path of monotonic static gates must alternate with LS and HS gates, just like domino logic must alternate with inverting dynamic and static gates [9]. Thus, a LS gate can only drive a HS gate and vice-versa.…”

Low-power comparator design based on CMOS dynamic logic circuit

“…Previously Static CMOS circuits [9] were used which found to be slow as each signal has to drive both NMOS & PMOS transistor which in turn increases power consumption so to overcome that Dynamic logic was introduced which works or operates only NMOS transistors which in turn increases the speed and hence improves the overall performance of circuit. Many researchers are working in this field just to improve the performance [3], [6], [7], [8] and its wide applications which just not only includes microprocessor but DSP (Digital Signal Processing) and Memory too.…”

Timing-driven partitioning for two-phase domino and mixed static/domino implementations

“…Domino synthesis has been an active area of recent research. In [3], a domino logic synthesis flow including logic optimization and technology mapping is described, and in [4,5], domino gate synthesis methods are described. The work in [6] addresses the problem of output phase assignment to minimize the duplication overhead required to make a network unate so that it may be implemented in domino logic.…”