Articles you may be interested inGe-stabilized tetragonal ZrO 2 as gate dielectric for Ge metal-oxide-semiconductor capacitors fabricated on Si substrate Appl. Phys. Lett. 97, 043503 (2010); 10.1063/1.3455904Damage-free metal-oxide-semiconductor gate electrode patterning on thin HfSiON film using neutral beam etching J.

The insertion of the CeO2 intermediate layer between the TiO2 layer and the Si substrate reduced the leakage current significantly after rapid thermal annealing (RTA) in O2 ambient for 3 min. After RTA, the TiO2/CeO2/Si structure showed a significantly lower leakage current than the TiO2/Si structure. At a proper voltage of −2 V, which was defined as the difference between the applied gate bias and the flatband voltage, the leakage current density of the TiO2/CeO2/Si structure was ∼10−8 A/cm2, while the leakage current density of the TiO2/Si sample was ∼10−2 A/cm2. The formation of the intermixed structure of TiO2 and CeO2 at the TiO2/CeO2 interface by RTA was thought to contribute to the reduction of the leakage current.

Properties of the HfO2/Hf-silicate/Si structure with the Hf-silicate layer which was formed by Hf metal deposition on Si and subsequent reaction of Hf with Si and oxygen during the HfO2 deposition were studied. Post-deposition N2 annealing reduced the equivalent oxide thickness (EOT) value and improved leakage characteristics of the HfO2/Hf-silicate/Si structure. The EOT value was reduced from 2.70 nm to 2.23 nm after annealing. At a proper voltage of 2.5 V, which was defined as the difference between the applied gate bias and the flat band voltage, the leakage current density of annealed HfO2/Hf-silicate/Si structure was 1.88×10-7 A/cm2 while that of as-formed HfO2/Hf-silicate/Si structure was 1.92×10-6 A/cm2. The breakdown field increased from 7.29 MV/cm to 9.71 MV/cm after annealing.