This paper presents an efficient parallel architecture for the real-time multimedia platform using multiple multimedia video processors (MVP; TMS32OC8O), which are fully programmable general-purpose digital signal processors (DSP). We have implemented an efficient parallel system, called the KAIST Image Computing System (KICS) for a multimedia platform and an image processing system. The main architecture of the KICS is a message passing model with hierarchically segmented buses. There are two parallel clusters in which two PE's (Processing Elements) are pipelined and the master PE of each cluster can access common global memory at high speed. The applications of the KICS to the MPEG-2 encoder and the volume rendering are introduced. The implemented algorithms are functionally or spatially partitioned and assigned to each PE in consideration with the load balancing and the required data traffic between PE's. The performance analysis for the applications and the general image processing functions are performed. The programmability and the highspeed data-access capability of the KICS are its most important features as a high-performance system for real-time multimedia data processing.
This paper presents the efficient algorithm mapping for the real-time MPEG-2 encoding on the KAIST Image Computing System (KICS), which has a parallel architecture using five multimedia video processors (MVP's). The MVP is a general purpose digital signal processor (DSP) of Texas Instrument. It combines one floating-point processor and four fixedpoint DSP's on a single chip. The KICS uses the MVP as a primary processing element (PE). Two PE's form a cluster, and there are two processing clusters in the KICS. Real-time MPEG-2 encoder is implemented through the spatial and the functional partitioning strategies. Encoding process of spatially partitioned half of the video input frame is assigned to one processing cluster. Two PE's perform the functionally partitioned MPEG-2 encoding tasks in the pipelined operation mode. One PE of a cluster carries out the transform coding part and the other performs the predictive coding part of the MPEG-2 encoding algorithm. One MVP among five MVP's is used for system control and interface with host computer. This paper introduces an implementation ofthe MPEG-2 algorithm with a parallel processing architecture.
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