This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 m CMOS process with a die size of 800 800 m 2 . Measurement results show that the total power consumption of the tag chip is only 7.4 W with a sensitivity of -12 dBm.
The quantization noise leakage of the first stage in a MASH21 sigma-delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion. The relationship between DC gain and leakage is modeled and conclusions on design criteria are reached. As an example, a MASH21 modulator for a digital audio application is realized. This modulator, fabricated in an 0.18 m mixed signal process, achieves an SNDR of 91 dB with 1.8 V supply, which verifies the analysis and design criteria.
This paper introduces a new method for SC sigma-delta modulator modeling. It studies the integrator's different equivalent circuits in the integrating and sampling phases. This model uses the OP-AMP input pair's tail current (I 0 / and overdrive voltage (v on / as variables. The modulator's static and dynamic errors are analyzed. A group of optimized I 0 and v on for maximum SNR and power area ratio can be obtained through this model. As examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively, which verifies the modeling and design criteria.
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