Design and implementation of an ultra-low power passive UHF RFID tag

Abstract

This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 m CMOS process with a die size of 800 800 m 2 . Measurement results show that the total power consumption of the tag chip is only 7.4 W with a sensitivity of -12 dBm.

Architecture Characteristics and Technical Trends of UHF RFID Temperature Sensor Chip

“…The digital baseband mainly implements communication protocols, encryption and decryption, encoding, decoding, anticollision algorithms, and operation control [53]. The digital demodulator detects and demodulates the signal from the RF analog front-end [7,9].…”

Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

“…The rectifier in Ref. [5] is implemented using Schottky diodes, which is based on the Dickson charge pump. The power conversion efficiency (PCE) is less than 35%.…”

“…Compared with the works in Refs. [5][6][7], we realize a high efficiency energy harvesting chain in this paper. In order to extend the maximum communication distance of the tag, a high efficiency differential CMOS rectifier circuit is adopted.…”