A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of −13.5 dBm
This paper presents a passive UHF RFID tag with a dynamic-V th -cancellation (DVC) rectifier. In the rectifier, the threshold voltages of MOSFETs are cancelled by applying gate bias voltages, which are dynamically changed according to the states of the MOSFETs. The DVC rectifier enables both low ON-resistance and small reverse leakage of the MOSFETs, resulting in high power conversion efficiency (PCE). An area-efficient demodulator with a novel average detector is also designed, which takes advantage of the rectifier's first stage as the envelope detector. The whole tag chip is implemented in a 0.18 m CMOS process with a die size of 880 950 m 2 . Measurement results show that the rectifier achieves a maximum PCE of 53.7% with 80 k resistor load.
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