Study and analysis of coefficient mismatch in a MASH21 sigma-delta modulator

Binjie, Ge; Wang, Xinan; Zhang, Xing; Xiaoxing, Feng; Wang, Qingqin

doi:10.1088/1674-4926/31/1/015007

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…With MATLAB modeling, NMOS and PMOS transistor in CMOS switch are 4 and 8 μm. With a large range scanning analysis, the opamp's design specifications can be acquired as listed in Table 3 [12] . This paper's modulator is a single loop structure, so there is no trans function mismatch issue between analog and digital circuit [13] , and low DC gain opamp can be employed, here folded-cascoded opamp is used for three integrators [14] .…”

Section: System Simulation and Modelingmentioning

confidence: 99%

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

Binjie¹,

Li²,

Yu³

et al. 2018

J. Semicond.

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This paper presents the design and implementation of quadrature bandpass sigma-delta modulator. A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and -1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2.

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Section: System Simulation and Modelingmentioning

confidence: 99%

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

Binjie¹,

Li²,

Yu³

et al. 2018

J. Semicond.

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show abstract

“…These nodes' transient expressions can be obtained from these equations OE4 , which are expressed as Eqs. ( 6) and (7).…”

Section: Modulator Transient Modelingmentioning

confidence: 99%

Sigma–delta modulator modeling analysis and design

et al. 2010

Self Cite

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This paper introduces a new method for SC sigma-delta modulator modeling. It studies the integrator's different equivalent circuits in the integrating and sampling phases. This model uses the OP-AMP input pair's tail current (I 0 / and overdrive voltage (v on / as variables. The modulator's static and dynamic errors are analyzed. A group of optimized I 0 and v on for maximum SNR and power area ratio can be obtained through this model. As examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively, which verifies the modeling and design criteria.

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Ultra-high resolution A/D converters Analysis, modeling and optimization tools

Maréchal¹

2014

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Study and analysis of coefficient mismatch in a MASH21 sigma-delta modulator

Cited by 3 publications

References 6 publications

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

Sigma–delta modulator modeling analysis and design

Ultra-high resolution A/D converters Analysis, modeling and optimization tools

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