This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kn L-resistor hardening scheme provides greater than 24-fold improvement in critical charge over a significant part of the sensing period. Also proposed is a novel single event (SE) mirroring concept for SEU hardening of DRAMS. This concept has been implemented for hardening the bitlines to hits on diffusion regions connected to the lines during the highly susceptible highimpedance state of the bitlines. It is shown to result in over 26-fold improvement in the level of critical charge using a 2pF dynamic capacitive coupling.
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a selfcompensating state while the cell is in standby mode. The proposed cell is comparable in size to a conventional DRAM cell, and computer simulations show an improvement in critical charge of two orders of magnitude over conventional l-T DRAM cells.
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