Single event mirroring and DRAM sense amplifier designs for improved single-event-upset performance

Abstract

This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kn L-resistor hardening scheme provides greater than 24-fold improvement in critical charge over a significant part of the sensing period. Also proposed is a novel single event (SE) mirroring concept for SEU hardening of DRAMS. This concept has been implemented for hardening the bitlines to hits on diffusion regions connected to the lines during the highly susceptible highimpedance state of the bitlines. It is shown to result in over 26-fold improvement in the level of critical charge using a 2pF dynamic capacitive coupling.

Basic mechanisms and modeling of single-event upset in digital microelectronics

“…For example, if the current is based on device simulations of a struck, unloaded device [152], then the circuit simulation inherits the inaccuracy of the improperly loaded device simulation. Still, circuit simulations have provided considerable insight into SEU in memories and have resulted in improvements to hardening techniques for a variety of circuits [12], [87], [103], [153], [154].…”

A radiation-hardened programmable read only memory for space applications

“…4(b)), which can provide double redundancy and improve the robustness. Secondly, according to [6,7], traditional sense amplifier designed with current mirror are the most radiation-sensitive parts of antifuse PROMs, so it should be excluded. Inverter is used as the sense amplifier in this design due to its robustness.…”

Cosmic and terrestrial single-event radiation effects in dynamic random access memories

“…Fig. 25 [89] circuit technique is implemented for the explicit task of reducing single-event bit-line errors in low-voltage DRAM circuits.…”