A proposed SEU tolerant dynamic random access memory (DRAM) cell

Agrawal, G.R.; Massengill, L.W.; Gulati, Kush

doi:10.1109/23.340539

Cited by 18 publications

(6 citation statements)

References 5 publications

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“…Main memory reliability is a key design concern for any system because when and how memory errors occur a ects overall system reliability. In particular, designers of reliabilitycritical systems such as enterprise-class computing clusters (e.g., cloud, HPC) and systems operating in extreme or hostile environments (e.g., military, automotive, industrial, extraterrestrial) take additional measures (e.g., custom components [46,47,[302][303][304][305][306][307][308], redundant resources [60,309,310]) to ensure that memory errors do not compromise their systems. Section 2.1.1 shows the bene ts of incorporating mechanisms to improve memory reliability.…”

Section: Study 1: Improving Memory Reliabilitymentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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Section: Study 1: Improving Memory Reliabilitymentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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“…Many papers report on experimental studies in the area of hardened logic circuits [17], [18], [5], [7], while others focus on radiation hardened memory designs [1], [2], [20], [21], [14]. Since memories are particularly susceptible to SEU/SET events, these efforts were crucial to space and military applications.…”

Section: Previous Workmentioning

confidence: 99%

A radiation tolerant Phase Locked Loop design for digital electronics

Kumar

Karkala

Garg

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this paper, we present a radiation hardened PLL design. Each of the components of this design -the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the loop filter are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our results demonstrate that over a large number of radiation strikes on a number of sensitive nodes in our design, the worst case jitter is just 18%. In the worst case, our PLL returns to the locked state in 16 cycles of the VCO clock, after a radiation strike.

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“…Several papers report on experimental studies in the area of hardened logic circuits [7], [2], [19], [5], [12], [15], while others have focused on radiation hardened memories [1], [2], [20], [21], [22], [23], [24], [25]. Since memories are particularly susceptible to SEU/SET events, these efforts were crucial to space and military applications.…”

Section: Previous Workmentioning

confidence: 99%

SEU hardened clock regeneration circuits

Dash

Garg

Khatri

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Single event upsets (SEUs) are becoming increasingly problematic for VLSI circuits due to device scaling, decreasing supply voltages and increasing operating frequencies.To deal with SEUs, radiation hardening is often employed to increase the reliability of VLSI systems. Most existing radiation hardening approaches focus on the combinational or sequential part of the design. Little or no attention has been paid to the impact of radiation particle strikes on the clock network of an IC. Recently, it has been shown that in the deep submicron regime, radiation particle strikes on clock networks can prove to be catastrophic. As a result, the clock network contributes significantl to the chip level Soft Error Rate (SER). In this paper, we present two SEU hardened clock regenerator designs which are immune to radiation particle strikes. The new designs result in a significan reduction in SEU induced clock jitter. Experimental results demonstrate that our clock regenerator hardening approaches reduce the radiation induced jitter to around 30ps and completely eliminates radiation induced voltage glitches, for radiation strikes with a deposited charge of up to 150fC.

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A proposed SEU tolerant dynamic random access memory (DRAM) cell

Cited by 18 publications

References 5 publications

A Case for Transparent Reliability in DRAM Systems

A Case for Transparent Reliability in DRAM Systems

A radiation tolerant Phase Locked Loop design for digital electronics

SEU hardened clock regeneration circuits

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