Single event upsets (SEUs) are becoming increasingly problematic for VLSI circuits due to device scaling, decreasing supply voltages and increasing operating frequencies.To deal with SEUs, radiation hardening is often employed to increase the reliability of VLSI systems. Most existing radiation hardening approaches focus on the combinational or sequential part of the design. Little or no attention has been paid to the impact of radiation particle strikes on the clock network of an IC. Recently, it has been shown that in the deep submicron regime, radiation particle strikes on clock networks can prove to be catastrophic. As a result, the clock network contributes significantl to the chip level Soft Error Rate (SER). In this paper, we present two SEU hardened clock regenerator designs which are immune to radiation particle strikes. The new designs result in a significan reduction in SEU induced clock jitter. Experimental results demonstrate that our clock regenerator hardening approaches reduce the radiation induced jitter to around 30ps and completely eliminates radiation induced voltage glitches, for radiation strikes with a deposited charge of up to 150fC.
Abstract-MIMO systems (with multiple transmit and receive antennas) are becoming increasingly popular, and many next-generation systems such as WiMAX, 3-GPP LTE and IEEE802.11n wireless LANs rely on the increased throughput of MIMO systems with up to four antennas at receiver and transmitter. High throughput implementation of the detection unit for MIMO systems is a significant challenge. This challenge becomes still harder, because the above mentioned standards demand support for multiple modulation and coding schemes. This implies that the MIMO detector must be dynamically reconfigurable. Also, to achieve required Bit Error Rate(BER) or Frame Error Rate (FER) performance, the detector has to provide soft values to advanced Forward Error Correction (FEC) schemes like Turbo Codes. This paper presents an ASIC implementation of a novel MIMO detector architecture that is able to reconfigure on the fly and provides soft values as output. The design is implemented in 45nm predictive technology library [16], and has a parallelism factor of four. The detector has many qualities of a systolic architecture and achieves a continuous throughput of 1Gbps for QPSK, 500Mbps for 16-QAM, and 187.5Mbps for 64-QAM. The total area is estimated to be approximately 70KGates equivalent, and power consumption is estimated to be 114mW.
Upcoming wireless communication standards such as 802.11n, WiMax etc require support for multiple modulation schemes. These standards all have multiple transmit and receive antennas(MIMO). Hence, the MIMO detector hardware should be able to accommodate different modulation schemes preferably on a single reconfigurable architecture. This paper presents an high performance FPGA implementation of a novel MIMO detector architecture that is able to reconfigure on the fly and provides quasi-optimal Bit Error Rate(BER). The design is implemented in Xilinx Virtex-4, and achieves a sustained throughput of 1.72Gbps for QPSK, 860Mbps for 16-QAM, and 430Mbps for 64-QAM. The total area is approximately 140.26KGates equivalent.Index Terms-MIMO systems, Fixed Sphere Decoding (FSD) Algorithm, On-the-fly Reconfigurability,802.11n. I. EXTENDED SUMMARY A. IntroductionTill date very few dynamically reconfigurable MIMO detectors have been reported in open literature. One implementation that supports reconfiguration is given in [6]. However, the authors in [6] use VBLAST based detection scheme that incurs significant BER degradation and an expensive processor based control unit to manage reconfigurability. Moreover, the design in [6] incurs significant reconfiguration latency which results in interruptions while switching between different modulation schemes. Authors in [7] present a design that is not dynamically reconfigurable. Our detector supports on the fly reconfigurability for QPSK, 16-QAM and 64-QAM modulation schemes. It delivers quasi-ML BER performance with no reconfiguration latency, leading to uninterrupted detection of MIMO symbols. B. MIMO DetectionThe baseband system model for a MIMO system with M T transmit and M R receive antennas can be expressed as follows [1].where s is M T × 1 transmitted vector or vector symbol, n is M R × 1 zero mean complex Gaussian noise vector, and H is a M R × M T -dimensional complex matrix. The (i, j) th element, h ij , of the matrix H denotes the complex channel gain from the j th transmit antenna to the i th receive antenna. In this paper we will assume M T = M R = 4, unless specified otherwise.The objective of the MIMO detection algorithm is to compute an estimateŝ of s such that:where Ω is set of complex entries from the QAM constellation and η is the cardinality of the set Ω.where, R is an upper triangular matrix, and Q H is the Hermitian of a unitary matrix Q[5]. Note that (3) can now be rewritten to form summation across each transmit antenna.
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