SEU hardened clock regeneration circuits

Abstract

Single event upsets (SEUs) are becoming increasingly problematic for VLSI circuits due to device scaling, decreasing supply voltages and increasing operating frequencies.To deal with SEUs, radiation hardening is often employed to increase the reliability of VLSI systems. Most existing radiation hardening approaches focus on the combinational or sequential part of the design. Little or no attention has been paid to the impact of radiation particle strikes on the clock network of an IC. Recently, it has been shown that in the deep submicron regime, radiation particle strikes on clock networks can prove to be catastrophic. As a result, the clock network contributes significantl to the chip level Soft Error Rate (SER). In this paper, we present two SEU hardened clock regenerator designs which are immune to radiation particle strikes. The new designs result in a significan reduction in SEU induced clock jitter. Experimental results demonstrate that our clock regenerator hardening approaches reduce the radiation induced jitter to around 30ps and completely eliminates radiation induced voltage glitches, for radiation strikes with a deposited charge of up to 150fC.

SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies

“…After generating a SET, the transient pulse can propagate through the clock buffers and clock gates depending on the width, the amplitude [7], and the size of the transistor [8]. SET effects can perturb the clock signal generating glitches, jitter [9] and clock skew [10] [13]. Finally the SET may reach one or more registers and change the value of stored data, resulting in a SEU or bit-flip.…”

“…Some techniques have been proposed about radiation hardening in clock buffers like a Hardened Dual Port Inverter [10], SEU Hardened Clock Leaf Inverter [11], and TMR Clock Regenerator Circuit [9]. However, these related works do not always consider in their SET evaluation analysis the variety of parameters in the clock network, such as sizes and types of buffers, the real fan-out of each buffer, clock gating and the capacitance and resistance of the paths.…”

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

“…It has been shown that clock distribution networks (CDNs) are becoming increasingly vulnerable to transient faults known as single event transients (SETs), owing to technology scaling [1]. In the deep submicron regime, CDNs contribute significantly to the chip-level soft error rate (SER) [2] and radiation particle strikes on the CDN can prove to be catastrophic [3]. Abnormal behaviors in the whole system may be generated if the clock signal is altered by radiation effects [4,5].…”

“…Although hardening techniques for sequential and combinational circuits have been studied extensively in the past, few research efforts have addressed the problem of radiation hardening in the CDN of an integrated circuit (IC). In the few existing hardened clock circuit designs, Dash et al [3] introduced the triple modulo redundancy (TMR) and split-output single event upset (SEU)-tolerant inverter approaches in the clock regeneration circuit. The split-output-based hardened regenerator will bring about extra delay, reduce the voltage swing, change the duty cycle of the clock signal, and may produce a high-impedance state.…”

“…In addition, the pulse width of the SETs that can be filtered is strongly dependent on the delay element. All of the techniques in [3,6] can only be applied at the leaf node of the CDN and they all suffer from large area overhead, high power consumption, and high complexity. Moreover, in [3,6], only single event single transients (SESTs) [7] of hardened leaf node circuits were simulated and evaluated, whereas the charge sharing effect and application of these hardening techniques in actual CDN design were not mentioned.…”