The current technology revolution in automobile industry is the autonomous vehicle wherein the vehicle without any intervention from the human driver responds to all kind of external conditions and performs all necessary functions that a human driver would perform while driving. Traffic sign identification is a crucial task in an autonomous driving system and even a minute misinterpretation could turn into a fatal one. This paper proposes a CNN based image classification which specifically uses pre-trained feature generated neural networks present in GoogleNet. GoogleNet is a CNN which recognizes the traffic signboards present by the roadside and sends the control signal to a microcontroller (Arduino Board) which controls the speed and the steering of the vehicle. The implemented CNN based automatic speed and steering control has been verified with a greater accuracy. The work presented in this paper leads towards the development of smart and sustainable cities under the Smart Cities Mission of India.
<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.</span>
<span lang="EN-US">The technology shrinkage and the increased demand for high storage memory devices in today’s system on-chips (SoCs) has been the challenges to the designers not only in the design cycle but also to the test engineers in testing these memory devices against the permanent faults, intermittent and soft errors. Around 90% of the chip area in today’s SoCs is being occupied by the embedded memories, and the cost for testing these memory devices contributes a major factor in the overall cost and the time to market. This paper</span><span lang="EN-US">proposes a strategy to develop a word-oriented March SS algorithm-basedmemory built-in self-test (MBIST), which is then applied for memory built-in self-test and repair (MBISTR) strategy. The implementation details for 1 KB of single-port static random-access memory (SRAM) depict that the modified March-SS algorithm based MBISTR-enabled SRAM facilitates self-test and self-repair of embedded memories with a marginal hardware overhead (<1%) in terms of look up tables and slice registers when compared to that of standard SRAM.</span>
In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX Reduced Instruction Set Computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults.
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