Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair

Acharya, G. Prasad; Rani, M. Asha; Kumar, Ganjikunta Ganesh; Poluboyina, Lavanya

doi:10.11591/ijeecs.v26.i1.pp96-104

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…From Table 1, it is clear that this method can correct either single bit error or three adjacent errors in 8-bit erroneous data read from memory. In method -2 tries to improve the number of bits corrected by modifying the way the erroneous bits are decoded [25,26]. The hamming bits are also used for decoding in addition to extended hamming bits and vertical parity bits.…”

Section: Methodsmentioning

confidence: 99%

Modified Matrix Codes for Shielding Memories Against Adjacent Errors

Subhas

2024

AEJ

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Soft errors are caused in memories due to radiation effects as the technology scales down. This paper concentrates on correcting adjacent errors in memories using indirect decoding mechanisms. Several matrix codes were also used to correct a maximum of two adjacent and random errors. In this paper, matrix representation of two rows for half the data bits matrix representations is used and each row is encoded with extended hamming code parity bits. Three ways of decoding are proposed. Among them, the method-1 uses only extended hamming bits of rows and vertical parity bits for decoding which is capable of correcting odd number of adjacent bits in half of data bits. The method-2 uses all parity bits and is capable of correcting 1 bit less than half the data bits. The method-3 uses all parity bits and with a change in decoding mechanism allows correction of half erroneous data bits. The method-3 based decoder proves to be more reliable either in lower half or upper half of Data, enabling it to be used in image processing applications. But method-3 compromises with decrease in code rate, increase in bit overhead, area and power delay product by atleast 26.38%, 10.76%, 9.6% and 5%.

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Section: Methodsmentioning

confidence: 99%

Modified Matrix Codes for Shielding Memories Against Adjacent Errors

Subhas

2024

AEJ

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“…Furthermore, the fault coverage achievable using it is higher than the MATS++ algorithm. e) March SS [51]…”

Section: New Algorithmsmentioning

confidence: 97%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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“…Architectures presented in [38], [39], [41], [43], [46] also used separate memory to implement redundancy to correct faults in main memories. Liu et al [40] use a different approach to improve the system's robustness when encountering stuck faults on embedded SRAMs.…”

Section: Using Separate Memory For Redundancy Instead Of Spare Rows/c...mentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair

Cited by 3 publications

References 6 publications

Modified Matrix Codes for Shielding Memories Against Adjacent Errors

Modified Matrix Codes for Shielding Memories Against Adjacent Errors

Testing nanometer memories: a review of architectures, applications, and challenges

Memory built-in self-repair and correction for improving yield: a review

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