Survey of test strategies for System-on Chip and it's embedded memories

Acharya, G. Prasad; Rani, M. Asha

doi:10.1109/raics.2013.6745473

Cited by 7 publications

(4 citation statements)

References 28 publications

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“…A survey on memory built-in self-repair architectures is presented in [12]. It mainly surveys memory testing methods and contains a small section on repair architectures.…”

Section: Previous Surveys On Memory Repairmentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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“…A survey on memory built-in self-repair architectures is presented in [12]. It mainly surveys memory testing methods and contains a small section on repair architectures.…”

Section: Previous Surveys On Memory Repairmentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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“…It also discussed future challenges regarding reducing voltage, increasing operation frequency, and process, voltage, and temperature (PVT) variations. Another survey was presented in [8], which discussed a few MBIST architectures and algorithms. Both these surveys were presented in 2013.…”

Section: Previous Surveys On Memory Testingmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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“…The March algorithms are more suitable for fault diagnosis and self-testing of regular 2-D memory architectures. March algorithms [11]- [14] performs March operations (memory write, and memory read operations) in a predefined sequence (ascending or descending order) of memory addressing. Each March operation could be: i) Write 0 (W0) into a memory cell.…”

Section: Introductionmentioning

confidence: 99%

Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair

Acharya¹,

Rani

Kumar³

et al. 2022

IJEECS

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<span lang="EN-US">The technology shrinkage and the increased demand for high storage memory devices in today’s system on-chips (SoCs) has been the challenges to the designers not only in the design cycle but also to the test engineers in testing these memory devices against the permanent faults, intermittent and soft errors. Around 90% of the chip area in today’s SoCs is being occupied by the embedded memories, and the cost for testing these memory devices contributes a major factor in the overall cost and the time to market. This paper</span><span lang="EN-US">proposes a strategy to develop a word-oriented March SS algorithm-basedmemory built-in self-test (MBIST), which is then applied for memory built-in self-test and repair (MBISTR) strategy. The implementation details for 1 KB of single-port static random-access memory (SRAM) depict that the modified March-SS algorithm based MBISTR-enabled SRAM facilitates self-test and self-repair of embedded memories with a marginal hardware overhead (<1%) in terms of look up tables and slice registers when compared to that of standard SRAM.</span>

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Survey of test strategies for System-on Chip and it's embedded memories

Cited by 7 publications

References 28 publications

Memory built-in self-repair and correction for improving yield: a review

Memory built-in self-repair and correction for improving yield: a review

Testing nanometer memories: a review of architectures, applications, and challenges

Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair

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