A two-chip accelerometer system has been designed, manufactured, and assembled in a standard dual-in-line plastic package. A capacitive sensing element is built on one chip and signal processing circuitry on a separate chip. The sensing element is designed in the form of a differential capacitor pair made from three highly doped polysilicon layers using surface micromachining technology. The circuitry is fabricated using a 1.75 ~tm CMOS technology and includes amplification, EPROM trim, filtering, and self-test functions. The system is designed for 50 g full scale acceleration, and operates in an open loop mode.
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IntroductionCurrent efforts to develop silicon-based accelerometers are driven by high volume applications in the automotive industry. These include ride control, inertial navigation, and crash sensing for airbag deployment. In each of these applications, reliability, self-diagnostics, and low cost are key requirements. Large-scale mechanical devices are not capable of meeting all these requirements. It is thus not surprising that the development of micromechanical accelerometers is one of the most aggressively pursued and challenging tasks in the sensor arena.To meet the challenge, designers have tried approaches based on piezoresistive [Tsugai and
A multicomponent mathematical model incorporating simultaneous Knudsen diffusion and heterogeneous reaction in a feature of arbitrary geometry has been developed to quantitatively predict step coverage in LPCVD. The single component model reveals that for a given CVD chemistry and feature geometry, deposition uniformity is controlled by a single parameter called the step coverage modulus. In multicomponent systems, each additional reactant partial pressure dependence in the deposition rate expression introduces an additional parameter equal to the ratio of the initial reactant partial pressures. Manipulation of the instantaneous step coverage modulus, through time variations of temperature and/or pressure results in higher average film growth rates without incurring a penalty in step coverage over patterned regions of the wafer. For deposition of SiO2 from TEOS, the step coverage modulus is varied through a time dependent temperature path. The path is chosen by constraining the deposition rate in the feature such that it varies by less than a few percent from top to bottom. For deposition of SiO2 from SiH4/O2, silane partial pressure is varied since the reaction rate is relatively insensitive to temperature. In each case. time savings of approximately 50% are achieved.
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