We characterized the oxide thickness of MOS capacitors fabricated on the high index silicon surfaces (1 1 4) and (5 5 12). The low index silicon wafers (0 0 1), (1 1 1), and (1 1 0) were used as a reference. Four fabrication processes were conducted, two with polysilicon gate (600Å oxide thickness), and two using aluminum gate (600Å and 150 Å oxide thickness). Our results show that the oxide thickness increases as the surface goes from (0 0 1) to (1 1 1).
We have fabricated, electrically characterized and simulated n-type hydrogenated amorphous silicon germanium alloys on p-type crystalline-silicon heterojunction diodes with three different a-SiGe:H layer thicknesses: 37, 86, and 200nm. The capacitance–voltage results confirm the existence of abrupt heterojunctions. The conduction and valence-band discontinuities of the heterojunctions and the electron affinity of the n-type a-SiGe:H films were obtained. The conduction mechanisms were determined by analyzing the temperature dependence of the current–voltage characteristics. The results show that at low forward bias (V<0.45V) the diodes with thinner amorphous layers (37 and 86nm) are dominated by recombination in the a-SiGe:H depletion region, whereas the thicker diode (200nm) is dominated by multistep tunneling through depletion region. In addition, at high forward bias (V>0.45V) the space-charge limited effect becomes the main transport mechanism in all the measured devices. The increase in the amorphous layer thickness also causes an increase in the leakage reverse current. Numerical simulations support the proposed transport mechanisms.
n-type a-SiGe:H on p-type c-Silicon heterojunctions were fabricated and electrically characterized. The transport mechanisms were determined by analyzing the temperature dependence of the current-voltage characteristics in two different wafers, with and without thermal annealing at 150 ºC. At low forward bias (V < 0.5 V), we found that the transport mechanisms are determined by the c-Si in both wafers. The ideality factors were 1.10 and 1.47 for the wafers, with and without low thermal annealing, respectively. At high forward bias (V 0.5 V), the space charge limited effect became the dominant transport mechanism in all the measured devices. Under reverse bias conditions, the J-V curves showed that the current density is dominated by the carrier generation.
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