The goal of thermal management is to meet maximum operating temperature constraints, while at the same time tracking timevarying performance requirements. Current approaches avoid thermal violations by forcing abrupt operating points changes (e.g. processor shutdown), which cause sharp performance degradation. In this paper we aim at achieving a smooth thermal control action, that minimizes the variance of performance tracking error. We formulate this problem as a discrete-time optimal control problem, which can be solved using the theory and computational tools developed in the field of model-predictive control. Our optimization process considers the thermal profile of the system, its evolution over time, and time-varying workload requirements. Experimental results show that the proposed approach offers significant thermal balancing improvements over previous methods.

Meeting the temperature constraints and reducing the hot-spots are critical for achieving reliable and efficient operation of complex multi-core systems. The goal of thermal management is to meet maximum operating temperature constraints, while tracking timevarying performance requirements. Current approaches avoid thermal violations by forcing abrupt operating points changes, which cause sharp performance degradation. In this paper we aim at achieving an online smooth thermal control action, that minimizes the tracking error. We formulate this problem as a discrete-time optimal control problem, which can be solved via online by using an embedded convex optimization solver using a receding horizon approach. The optimization problem considers the thermal profile of the system, its evolution over time, current and past time-varying workload requirements. We perform experiments on a model of the 8-core Niagara-1 multicore architecture, which show that the proposed method outperforms state-of-the-art thermal management approaches by enabling performance speed-ups of up to 2.5× and improvements up to 12× and 3.4× in relation to frequency and temperature variations over time, respectively.

Abstract-Thermal balancing and reducing hot-spots are two important challenges facing the MPSoC designers. In this work, we model the thermal behavior of a MPSoC as a control theory problem which enables the design of an optimum frequency controller without depending on the thermal profile of the chip. The optimization performed by the controller is targeted to achieve thermal balancing on the MPSoC thermal profile to avoid hotspots and improve its reliability. The proposed system is able to perform an on-line minimization of chip thermal gradients based on both scheduler requirements and the chip thermal profile. We compare this with state of the art thermal management approaches. Our comparison shows that the proposed system offers a better both thermal profile (temperature differences higher than 4• C have been reduced from 27.9% to 0.45%) and performance (up to 32% task waiting time reduction).I. INTRODUCTION With the advance of technology, the number of functional units and cores integrated on a chip is increasing. Today, several commercial multi-core architectures with few cores to several tens of cores such as IBM's Cell [1], Sun's Niagara [2] and Tilera's 64-core architecture [3] are available. In order to implement these systems, semiconductor industry is facing several technological challenges. It is predicted that in the near future, peak power dissipation and consequent thermal implications will be a major performance bottleneck for multi-core systems [5]. Temperature gradients and hot-spots not only affect the performance of the system, but also lead to unreliable circuit operation and affect the life-time of the chip [4], thus thermal management/balancing for MPSoCs is a critical matter to tackle.In the last years, thermal management/balancing techniques received a lot of attention as a collateral effect of increasing power density. Adaptive mechanism focusing on handling key micro-architectural hotspots have been proposed in [9] and [14]. In [15] and [13] a significant reduction in localized hotspots has been obtained using thread migration techniques. The problem with these techniques is that they perform the optimization using task migration which requires extra operations to be performed and increases chip power consumption.Another way, less power consuming to perform thermal balancing is by employing dynamic frequency and voltage scaling (DVFS) based techniques. The idea has been proposed in several works [8] - [10]. The major problem of all these approaches is that they are targeting power density reductions with the effect of reducing overall temperature. However this

Abstract-Three-dimensional (3D) integrated circuits and systems are expected to be present in electronic products in the short term. We consider specifically 3D multi-processor systems-on-chips (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by means of through-silicon vias (TSVs). Because of the high power density of devices and interconnect in the 3D stack, thermal issues pose critical challenges, such as hot-spot avoidance and thermal gradient reduction. Thermal management is achieved by a combination of active control of on-chip switching rates as well as active interlayer cooling with pressurized fluids.In this paper, we propose a novel online thermal management policy for high-performance 3D systems with liquid cooling. Our proposed controller uses a hierarchical approach with a global controller regulating the active cooling and local controllers (on each layer) performing dynamic voltage and frequency scaling (DVFS) and interacting with the global controller. Then, the on-line control is achieved by policies that are computed off-line by solving an optimization problem that considers the thermal profile of 3D-MPSoCs, its evolution over time and current time-varying workload requirements. The proposed hierarchical scheme is scalable to complex (and heterogeneous) 3D chip stacks.We perform experiments on a 3D-MPSoC case study with different interlayer cooling structures, using benchmarks ranging from web-accessing to playing multimedia. Results show significant advantages in terms of energy savings that reaches values up to 50% versus state-of-the-art thermal control techniques for liquid cooling, and thermal balance with differences of less than 10 C per layer.Index Terms-Hardware/software co-design, multilayer, multiprocessor system-on-chip (SoC), power modeling and estimation, thermal.

Abstract-Multi-Processor Systems-on-Chip (MPSoCs) are penetrating the electronics market as a powerful, yet commercially viable, solution to answer the strong and steadily growing demand for scalable and high performance systems, at limited design complexity. However, it is critical to develop dedicated system-level design methodologies for multi-core architectures that seamlessly address their thermal modeling, analysis and management. In this work, we first formulate the problem of system-level thermal modeling and link it to produce a global thermal management formulation as a discrete-time optimal control problem, which can be solved using finite-horizon model-predictive control (MPC) techniques, while adapting to the actual time-varying unbalanced MPSoC workload requirements. Finally, we compare the system-level MPC-based thermal modeling and management approaches on an industrial 8-core MPSoC design and show their different trade-offs regarding performance while respecting operating temperature bounds.