Sub 200 nm wafer-to-wafer (w2w) overlay accuracy on the entire 300 mm wafer was successfully demonstrated via wafer level Cu/SiO 2 hybrid bonding. Cu bonding pads relevant for back-side illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS) were used for the experiment. Further, a crucial component to improve the overlay accuracy, namely the overlay model which identifies systematic alignment errors, was described. IntroductionThe growing demand for increased functionality and higher performance in integrated circuits (ICs) requires more transistors which means the transistor and interconnect size must decrease in order to maintain the same chip size (with respect to its lateral dimensions). Because of these factors different integration schemes like three-dimensional (3D) ICs with the purpose of reducing global interconnection length become more and more relevant for increased speed and operation frequency. W2w bonding is an attractive and crucial technique for enabling 3D integration. The bonding processes of fusion bonding and metal bonding, such as metal thermocompression, eutectic, and transient liquid phase (TLP) bonding, are well established and many of them are already in mass production [1][2][3][4]. The more recent approach of hybrid wafer level bonding is an attractive technique for reliably connecting heterogeneous structures, such as connecting processor with memory, analogue IC or microelectromechanical systems (MEMS), having high-density interconnects (<10 μm pitch). Within this work the bonding process for Cu/SiO 2 hybrid structures, which is an attractive material combination for BSI CIS, was investigated [5]. Furthermore, relevant changes to improve the w2w post-bond overlay accuracy are presented, as well as the overlay model which was introduced to isolate and quantify different global misalignment root causes, such as translation, rotation and scaling.
Substrate cleaning is a very important process step in direct wafer bonding. Current work describes development, testing and verification of a single wafer megasonic cleaning method utilizing a transducer design that meets the extreme particle neutrality, Particle Removal Efficiency (PRE), and repeatability requirements of production scale wafer bonding and other applications requiring extremely low particle levels. The results were obtained using 300 mm diameter Si wafer which were processed as received, without any wet bench cleaning process. These experiments simulated real case production scenario in which the particle counts on incoming wafers are typically 0.1 LPD/cm2 and lower.
Both fusion and hybrid wafer bonding are enabling increasing integration density as well as advanced device integration strategies. In any case, wafer-to-wafer overlay accuracy is the most critical factor for successful integration in 3D stacked devices. Despite alignment of both wafers is of major impact for the post-bond overlay accuracy, initiation and control of the bond wave between both substrate wafers the essential. During contacting device wafer surfaces, wafer stress as well as bow is influencing the bond wave dynamics. Engineering the continuous wave dynamics and influencing parameters are both key for optimum post-bond overlay accuracy. Any wafer stress will result into distortion of patterns and additional misalignment term. Despite typical distortion values are well below 50nm already, further optimization of both wafer bonding as well as wafer preparation and preprocessing are key for hybrid and monolithic integration.
The development of low temperature direct wafer bonding processes paved the way for new categories of applications based on semiconductor devices. Precise optical alignment of wafers prior wafer bonding plays a key role in manufacturing of current and future applications based on wafers stacking. In order to address the continuous feature size shrinking and increasing integration levels the need for high alignment accuracy imposed significant hardware and process improvements. The future microelectronics applications are foreseen to require wafer-to-wafer alignment accuracy as low as ±100 nm and better. This work reviews the main contributors to the misalignment budget and presents experimental alignment results for alignment accuracy in the range of 50 – 100 nm.
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